k3-j7200-evm is the new evaluation module from Texas Instruments which has the j7200 SoC. It has a dual coreARM Cortex-A72 CPU cores, 4GiB of RAM, 2x Display ports, 6x UART ports, 5x ethernet ports, SD and eMMC interfaces for storage and many other connectivity and accelerator devices.
J7200 TRM: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Nikhil Devshatwar <[email protected]> --- configs/arm64/k3-j7200-evm.c | 359 +++++++++++++++++++++++++++++++++++ 1 file changed, 359 insertions(+) create mode 100644 configs/arm64/k3-j7200-evm.c diff --git a/configs/arm64/k3-j7200-evm.c b/configs/arm64/k3-j7200-evm.c new file mode 100644 index 00000000..c3ac331d --- /dev/null +++ b/configs/arm64/k3-j7200-evm.c @@ -0,0 +1,359 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com/ + * + * Configuration for K3 based J7200-EVM + * + * Authors: + * Nikhil Devshatwar <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[32]; + struct jailhouse_irqchip irqchips[6]; + struct jailhouse_pci_device pci_devices[2]; + __u32 stream_ids[1]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, + .hypervisor_memory = { + .phys_start = 0x89fa00000, + .size = 0x400000, + }, + .debug_console = { + .address = 0x02800000, + .size = 0x1000, + .type = JAILHOUSE_CON_TYPE_8250, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_MDR_QUIRK | + JAILHOUSE_CON_REGDIST_4, + }, + .platform_info = { + .pci_mmconfig_base = 0x76000000, + .pci_mmconfig_end_bus = 0, + .pci_is_virtual = 1, + .pci_domain = 4, + .iommu_units = { + { + .type = JAILHOUSE_IOMMU_PVU, + .base = 0x30f80000, + .size = 0x1000, + .tipvu.tlb_base = 0x36000000, + .tipvu.tlb_size = 0x40000, + }, + { + .type = JAILHOUSE_IOMMU_PVU, + .base = 0x30f81000, + .size = 0x1000, + .tipvu.tlb_base = 0x36040000, + .tipvu.tlb_size = 0x40000, + }, + }, + .arm = { + .gic_version = 3, + .gicd_base = 0x01800000, + .gicr_base = 0x01900000, + .maintenance_irq = 25, + }, + }, + .root_cell = { + .name = "k3-j7200-evm", + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + .num_stream_ids = ARRAY_SIZE(config.stream_ids), + .vpci_irq_base = 191 - 32, + }, + }, + + .cpus = { + 0x3, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions for 00:00.0 (demo) */ + { + .phys_start = 0x89fe00000, + .virt_start = 0x89fe00000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0x89fe10000, + .virt_start = 0x89fe10000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0x89fe20000, + .virt_start = 0x89fe20000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0x89fe30000, + .virt_start = 0x89fe30000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ, + }, + /* IVSHMEM shared memory regions for 00:01.0 (networking) */ + JAILHOUSE_SHMEM_NET_REGIONS(0x89fe40000, 0), + /* ctrl mmr */ { + .phys_start = 0x00100000, + .virt_start = 0x00100000, + .size = 0x00020000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* gpio */ { + .phys_start = 0x00600000, + .virt_start = 0x00600000, + .size = 0x00032000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* serdes */ { + .phys_start = 0x00900000, + .virt_start = 0x00900000, + .size = 0x00012000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* timesync router */ { + .phys_start = 0x00A40000, + .virt_start = 0x00A40000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* Most peripherals */ { + .phys_start = 0x01000000, + .virt_start = 0x01000000, + .size = 0x0d000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MAIN NAVSS */ { + .phys_start = 0x30000000, + .virt_start = 0x30000000, + .size = 0x0c400000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MSMC SRAM */ { + .phys_start = 0x70000000, + .virt_start = 0x70000000, + .size = 0x00800000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe Core */ { + .phys_start = 0x18000000, + .virt_start = 0x18000000, + .size = 0x08000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* PCIe DAT */ { + .phys_start = 0x4100000000, + .virt_start = 0x4100000000, + .size = 0x100000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_DMA, + }, + /* C71 */ { + .phys_start = 0x64800000, + .virt_start = 0x64800000, + .size = 0x00800000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + + /* MCU NAVSS */ { + .phys_start = 0x28380000, + .virt_start = 0x28380000, + .size = 0x03880000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU First peripheral window */ { + .phys_start = 0x40200000, + .virt_start = 0x40200000, + .size = 0x00999000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU CTRL_MMR0 */ { + .phys_start = 0x40f00000, + .virt_start = 0x40f00000, + .size = 0x00020000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU R5F Core0 */ { + .phys_start = 0x41000000, + .virt_start = 0x41000000, + .size = 0x00020000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU R5F Core1 */ { + .phys_start = 0x41400000, + .virt_start = 0x41400000, + .size = 0x00020000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU SRAM */ { + .phys_start = 0x41c00000, + .virt_start = 0x41c00000, + .size = 0x00100000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_DMA, + }, + /* MCU WKUP peripheral window */ { + .phys_start = 0x42040000, + .virt_start = 0x42040000, + .size = 0x03ce4000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU CPSW */ { + .phys_start = 0x46000000, + .virt_start = 0x46000000, + .size = 0x00200000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU OSPI register space */ { + .phys_start = 0x47000000, + .virt_start = 0x47000000, + .size = 0x00069000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* MCU FSS OSPI0/1 data region 0 */ { + .phys_start = 0x50000000, + .virt_start = 0x50000000, + .size = 0x10000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_DMA, + }, + + /* RAM - first bank*/ { + .phys_start = 0x80000000, + .virt_start = 0x80000000, + .size = 0x80000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* RAM - second bank */ { + .phys_start = 0x880000000, + .virt_start = 0x880000000, + .size = 0x1fa00000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* RAM - reserved for baremetal apps */ { + .phys_start = 0x89ff40000, + .virt_start = 0x89ff40000, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* RAM - reserved for inmate */ { + .phys_start = 0x8a0000000, + .virt_start = 0x8a0000000, + .size = 0x60000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + }, + .irqchips = { + { + .address = 0x01800000, + .pin_base = 32, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x01800000, + .pin_base = 160, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x01800000, + .pin_base = 288, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x01800000, + .pin_base = 416, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x01800000, + .pin_base = 544, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + .address = 0x01800000, + .pin_base = 800, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + }, + + .pci_devices = { + /* 00:00.0 (demo) */ { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 4, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX_64K, + .shmem_regions_start = 0, + .shmem_dev_id = 0, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + /* 00:01.0 (networking) */ { + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 4, + .bdf = 1 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX_64K, + .shmem_regions_start = 4, + .shmem_dev_id = 0, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, + + .stream_ids = { + /* Non PCIe peripherals */ + 0x0002, + }, +}; -- 2.17.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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