On 08/11/2020 22:51, Jan Kiszka wrote:
> On 28.10.20 22:09, Andrea Bastoni wrote:
>> Signed-off-by: Andrea Bastoni <[email protected]>
>> ---
>> hypervisor/arch/x86/apic.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/hypervisor/arch/x86/apic.c b/hypervisor/arch/x86/apic.c
>> index d36c2033..b49a6745 100644
>> --- a/hypervisor/arch/x86/apic.c
>> +++ b/hypervisor/arch/x86/apic.c
>> @@ -315,7 +315,7 @@ void apic_clear(void)
>> {
>> unsigned int maxlvt = (apic_ops.read(APIC_REG_LVR) >> 16) & 0xff;
>> unsigned int xlc = (apic_ext_features() >> 16) & 0xff;
>> - int n;
>> + unsigned int n;
>>
>> /* Enable the APIC - the cell may have turned it off */
>> apic_ops.write(APIC_REG_SVR, APIC_SVR_ENABLE_APIC | 0xff);
>> @@ -336,7 +336,7 @@ void apic_clear(void)
>>
>> /* Clear ISR. This is done in reverse direction as EOI
>> * clears highest-priority interrupt ISR bit. */
>> - for (n = APIC_NUM_INT_REGS-1; n >= 0; n--)
>> + for (n = APIC_NUM_INT_REGS-1; n != 0; n--)
>
> That's not the same. Will follow up with then patch I modifed patch I
> applied.
Ouch I missed it. Thanks for fixing.
>
>> while (apic_ops.read(APIC_REG_ISR0 + n) != 0)
>> apic_ops.write(APIC_REG_EOI, APIC_EOI_ACK);
>>
>>
>
> Jan
>
--
Thanks,
Andrea Bastoni
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