From: Jan Kiszka <[email protected]> Derived from the arm64 QEMU target, this adds one for 32-bit ARM which also stresses the virtual GICv2. Works with QEMU 4.2.1 or newer.
Signed-off-by: Jan Kiszka <[email protected]> --- configs/arm/dts/inmate-qemu-arm.dts | 105 +++++++++++++++++++ configs/arm/qemu-arm-inmate-demo.c | 132 ++++++++++++++++++++++++ configs/arm/qemu-arm-linux-demo.c | 152 +++++++++++++++++++++++++++ configs/arm/qemu-arm.c | 154 ++++++++++++++++++++++++++++ 4 files changed, 543 insertions(+) create mode 100644 configs/arm/dts/inmate-qemu-arm.dts create mode 100644 configs/arm/qemu-arm-inmate-demo.c create mode 100644 configs/arm/qemu-arm-linux-demo.c create mode 100644 configs/arm/qemu-arm.c diff --git a/configs/arm/dts/inmate-qemu-arm.dts b/configs/arm/dts/inmate-qemu-arm.dts new file mode 100644 index 00000000..06e92912 --- /dev/null +++ b/configs/arm/dts/inmate-qemu-arm.dts @@ -0,0 +1,105 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Device tree for Linux inmate test on QEMU ARM target, + * corresponds to configs/arm/qemu-arm-linux-demo.c + * + * Copyright (c) Siemens AG, 2016-2020 + * + * Authors: + * Jan Kiszka <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/dts-v1/; + +/ { + model = "Jailhouse cell on QEMU ARM"; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + hypervisor { + compatible = "jailhouse,cell"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@2 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <3>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + gic: interrupt-controller@8000000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x08000000 0x1000>, /* GICD */ + <0x08010000 0x1000>; /* GICC */ + }; + + apb_pclk: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk24mhz"; + }; + + uart0: serial@9000000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x09000000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb_pclk>, <&apb_pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pci@7000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_EDGE_RISING>, + <0 0 0 2 &gic GIC_SPI 109 IRQ_TYPE_EDGE_RISING>, + <0 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, + <0 0 0 4 &gic GIC_SPI 111 IRQ_TYPE_EDGE_RISING>; + reg = <0x08e00000 0x100000>; + ranges = + <0x02000000 0x00 0x10000000 0x10000000 0x00 0x10000>; + }; +}; diff --git a/configs/arm/qemu-arm-inmate-demo.c b/configs/arm/qemu-arm-inmate-demo.c new file mode 100644 index 00000000..3f835d9e --- /dev/null +++ b/configs/arm/qemu-arm-inmate-demo.c @@ -0,0 +1,132 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Configuration for demo inmate on QEMU arm6virtual target + * 1 CPU, 64K RAM, 1 serial port + * + * Copyright (c) Siemens AG, 2017-2020 + * + * Authors: + * Jan Kiszka <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[8]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pci_device pci_devices[1]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "inmate-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + + .vpci_irq_base = 144-32, + + .console = { + .address = 0x09000000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0b0010, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions (demo) */ + { + .phys_start = 0x7faf0000, + .virt_start = 0x7faf0000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7faf1000, + .virt_start = 0x7faf1000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7fafa000, + .virt_start = 0x7fafa000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7fafc000, + .virt_start = 0x7fafc000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7fafe000, + .virt_start = 0x7fafe000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + /* UART */ { + .phys_start = 0x09000000, + .virt_start = 0x09000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ { + .phys_start = 0x7fa00000, + .virt_start = 0, + .size = 0x00010000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x08000000, + .pin_base = 32, + .pin_bitmap = { + 0, + 0, + 0, + (1 << (144 - 128)) + }, + }, + }, + + .pci_devices = { + { /* IVSHMEM (demo) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 1, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + }, +}; diff --git a/configs/arm/qemu-arm-linux-demo.c b/configs/arm/qemu-arm-linux-demo.c new file mode 100644 index 00000000..e0124baa --- /dev/null +++ b/configs/arm/qemu-arm-linux-demo.c @@ -0,0 +1,152 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Configuration for linux-demo inmate on QEMU arm: + * 2 CPUs, 128M RAM, serial port + * + * Copyright (c) Siemens AG, 2014-2020 + * + * Authors: + * Jan Kiszka <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_cell_desc cell; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[13]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pci_device pci_devices[2]; +} __attribute__((packed)) config = { + .cell = { + .signature = JAILHOUSE_CELL_DESC_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .name = "qemu-arm-linux-demo", + .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | + JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED, + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + + .vpci_irq_base = 140-32, + + .console = { + .address = 0x09000000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + }, + + .cpus = { + 0b1100, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions (demo) */ + { + .phys_start = 0x7faf0000, + .virt_start = 0x7faf0000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7faf1000, + .virt_start = 0x7faf1000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7fafa000, + .virt_start = 0x7fafa000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7fafc000, + .virt_start = 0x7fafc000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED, + }, + { + .phys_start = 0x7fafe000, + .virt_start = 0x7fafe000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_ROOTSHARED, + }, + /* IVSHMEM shared memory region */ + JAILHOUSE_SHMEM_NET_REGIONS(0x7fb00000, 1), + /* UART */ { + .phys_start = 0x09000000, + .virt_start = 0x09000000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, + }, + /* RAM */ { + .phys_start = 0x7f900000, + .virt_start = 0, + .size = 0x10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, + }, + /* RAM */ { + .phys_start = 0x70000000, + .virt_start = 0x70000000, + .size = 0x8000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | + JAILHOUSE_MEM_LOADABLE, + }, + /* communication region */ { + .virt_start = 0x80000000, + .size = 0x00001000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_COMM_REGION, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x08000000, + .pin_base = 32, + .pin_bitmap = { + 1 << (33 - 32), + 0, + 0, + (1 << (140 - 128)) | (1 << (141 - 128)) + }, + }, + }, + + .pci_devices = { + { /* IVSHMEM 00:00.0 (demo) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 2, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + { /* IVSHMEM 00:01.0 (networking) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .bdf = 1 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 5, + .shmem_dev_id = 1, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, +}; diff --git a/configs/arm/qemu-arm.c b/configs/arm/qemu-arm.c new file mode 100644 index 00000000..4a3eac7b --- /dev/null +++ b/configs/arm/qemu-arm.c @@ -0,0 +1,154 @@ +/* + * Jailhouse, a Linux-based partitioning hypervisor + * + * Configuration for QEMU arm virtual target, 1G RAM, 8 cores + * + * Copyright (c) Siemens AG, 2017-2020 + * + * Authors: + * Jan Kiszka <[email protected]> + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * NOTE: Add "mem=768M" to the kernel command line. + */ + +#include <jailhouse/types.h> +#include <jailhouse/cell-config.h> + +struct { + struct jailhouse_system header; + __u64 cpus[1]; + struct jailhouse_memory mem_regions[11]; + struct jailhouse_irqchip irqchips[1]; + struct jailhouse_pci_device pci_devices[2]; +} __attribute__((packed)) config = { + .header = { + .signature = JAILHOUSE_SYSTEM_SIGNATURE, + .revision = JAILHOUSE_CONFIG_REVISION, + .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE, + .hypervisor_memory = { + .phys_start = 0x7fc00000, + .size = 0x00400000, + }, + .debug_console = { + .address = 0x09000000, + .size = 0x1000, + .type = JAILHOUSE_CON_TYPE_PL011, + .flags = JAILHOUSE_CON_ACCESS_MMIO | + JAILHOUSE_CON_REGDIST_4, + }, + .platform_info = { + .pci_mmconfig_base = 0x08e00000, + .pci_mmconfig_end_bus = 0, + .pci_is_virtual = 1, + .pci_domain = 1, + .arm = { + .gic_version = 2, + .gicd_base = 0x08000000, + .gicc_base = 0x08010000, + .gich_base = 0x08030000, + .gicv_base = 0x08040000, + .maintenance_irq = 25, + }, + }, + .root_cell = { + .name = "qemu-arm", + + .cpu_set_size = sizeof(config.cpus), + .num_memory_regions = ARRAY_SIZE(config.mem_regions), + .num_irqchips = ARRAY_SIZE(config.irqchips), + .num_pci_devices = ARRAY_SIZE(config.pci_devices), + + .vpci_irq_base = 128-32, + }, + }, + + .cpus = { + 0xff, + }, + + .mem_regions = { + /* IVSHMEM shared memory regions for 00:00.0 (demo) */ + { + .phys_start = 0x7faf0000, + .virt_start = 0x7faf0000, + .size = 0x1000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0x7faf1000, + .virt_start = 0x7faf1000, + .size = 0x9000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0x7fafa000, + .virt_start = 0x7fafa000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE, + }, + { + .phys_start = 0x7fafc000, + .virt_start = 0x7fafc000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ, + }, + { + .phys_start = 0x7fafe000, + .virt_start = 0x7fafe000, + .size = 0x2000, + .flags = JAILHOUSE_MEM_READ, + }, + /* IVSHMEM shared memory regions for 00:01.0 (networking) */ + JAILHOUSE_SHMEM_NET_REGIONS(0x7fb00000, 0), + /* MMIO (permissive) */ { + .phys_start = 0x09000000, + .virt_start = 0x09000000, + .size = 0x37000000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_IO, + }, + /* RAM */ { + .phys_start = 0x40000000, + .virt_start = 0x40000000, + .size = 0x3fa10000, + .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | + JAILHOUSE_MEM_EXECUTE, + }, + }, + + .irqchips = { + /* GIC */ { + .address = 0x08000000, + .pin_base = 32, + .pin_bitmap = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + }, + + .pci_devices = { + { /* IVSHMEM 0001:00:00.0 (demo) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 0 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 0, + .shmem_dev_id = 0, + .shmem_peers = 3, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED, + }, + { /* IVSHMEM 0001:00:01.0 (networking) */ + .type = JAILHOUSE_PCI_TYPE_IVSHMEM, + .domain = 1, + .bdf = 1 << 3, + .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX, + .shmem_regions_start = 5, + .shmem_dev_id = 0, + .shmem_peers = 2, + .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, + }, + }, +}; -- 2.26.2 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/3cf261b06c63f165a48ad1671596e8eb7de4a3f0.1609752982.git.jan.kiszka%40web.de.
