From: Jan Kiszka <[email protected]> When in EL2, banked SPSR_hyp is not accessible. We rather want SPSR of the current mode. For writing, that means appending fsxc which selects all bits. Reading means dropping the bank suffix.
Noticed via QEMU. Real HW might have done the intended access so far. Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/arch/arm/control.c | 2 +- hypervisor/arch/arm/mmio.c | 4 ++-- hypervisor/arch/arm/setup.c | 2 +- hypervisor/arch/arm/traps.c | 10 +++++----- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hypervisor/arch/arm/control.c b/hypervisor/arch/arm/control.c index cd68dd9a..0e7a1b54 100644 --- a/hypervisor/arch/arm/control.c +++ b/hypervisor/arch/arm/control.c @@ -84,7 +84,7 @@ void arm_cpu_reset(unsigned long pc, bool aarch32) arm_write_sysreg(TPIDRURO, 0); arm_write_sysreg(TPIDRPRW, 0); - arm_write_banked_reg(SPSR_hyp, RESET_PSR); + arm_write_banked_reg(SPSR_fsxc, RESET_PSR); arm_write_banked_reg(ELR_hyp, pc); /* transfer the context that may have been passed to PSCI_CPU_ON */ diff --git a/hypervisor/arch/arm/mmio.c b/hypervisor/arch/arm/mmio.c index 1c492b43..0162bc7c 100644 --- a/hypervisor/arch/arm/mmio.c +++ b/hypervisor/arch/arm/mmio.c @@ -38,7 +38,7 @@ static void arch_inject_dabt(struct trap_context *ctx, unsigned long addr) arm_read_sysreg(TTBCR, ttbcr); arm_read_banked_reg(ELR_hyp, pc); - arm_read_banked_reg(SPSR_hyp, cpsr); + arm_read_banked_reg(SPSR, cpsr); /* Set cpsr */ is_thumb = cpsr & PSR_T_BIT; @@ -50,7 +50,7 @@ static void arch_inject_dabt(struct trap_context *ctx, unsigned long addr) if (sctlr & SCTLR_EE_BIT) cpsr |= PSR_E_BIT; - arm_write_banked_reg(SPSR_hyp, cpsr); + arm_write_banked_reg(SPSR_fsxc, cpsr); lr_offset = (is_thumb ? 4 : 0); arm_write_banked_reg(LR_abt, pc + lr_offset); diff --git a/hypervisor/arch/arm/setup.c b/hypervisor/arch/arm/setup.c index 115e76e8..adb56f58 100644 --- a/hypervisor/arch/arm/setup.c +++ b/hypervisor/arch/arm/setup.c @@ -79,7 +79,7 @@ cpu_prepare_return_el1(struct per_cpu *cpu_data, int return_code) asm volatile ( "msr sp_svc, %0\n\t" "msr elr_hyp, %1\n\t" - "msr spsr_hyp, %2\n\t" + "msr spsr_fsxc, %2\n\t" : : "r" (cpu_data->linux_sp + (NUM_ENTRY_REGS * sizeof(unsigned long))), diff --git a/hypervisor/arch/arm/traps.c b/hypervisor/arch/arm/traps.c index 10b3fdbf..6b402f74 100644 --- a/hypervisor/arch/arm/traps.c +++ b/hypervisor/arch/arm/traps.c @@ -55,7 +55,7 @@ static bool arch_failed_condition(struct trap_context *ctx) u32 iss = HSR_ISS(ctx->hsr); u32 cpsr, flags, cond; - arm_read_banked_reg(SPSR_hyp, cpsr); + arm_read_banked_reg(SPSR, cpsr); flags = cpsr >> 28; /* @@ -99,7 +99,7 @@ static void arch_advance_itstate(struct trap_context *ctx) unsigned long itbits, cond; u32 cpsr; - arm_read_banked_reg(SPSR_hyp, cpsr); + arm_read_banked_reg(SPSR, cpsr); if (!(cpsr & PSR_IT_MASK(0xff))) return; @@ -116,7 +116,7 @@ static void arch_advance_itstate(struct trap_context *ctx) cpsr &= ~PSR_IT_MASK(0xff); cpsr |= PSR_IT_MASK(itbits); - arm_write_banked_reg(SPSR_hyp, cpsr); + arm_write_banked_reg(SPSR_fsxc, cpsr); } void arch_skip_instruction(struct trap_context *ctx) @@ -151,7 +151,7 @@ void access_cell_reg(struct trap_context *ctx, u8 reg, unsigned long *val, { u32 mode; - arm_read_banked_reg(SPSR_hyp, mode); + arm_read_banked_reg(SPSR, mode); mode &= PSR_MODE_MASK; switch (reg) { @@ -234,7 +234,7 @@ static void dump_guest_regs(struct trap_context *ctx) u32 pc, cpsr; arm_read_banked_reg(ELR_hyp, pc); - arm_read_banked_reg(SPSR_hyp, cpsr); + arm_read_banked_reg(SPSR, cpsr); panic_printk("pc=0x%08x cpsr=0x%08x hsr=0x%08x\n", pc, cpsr, ctx->hsr); for (reg = 0; reg < 15; reg++) { access_cell_reg(ctx, reg, ®_val, true); -- 2.26.2 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/9638d507b2f979e0c46a3b557372166408f91b20.1609774199.git.jan.kiszka%40web.de.
