Remove the debug cache_layout autodetection, which could be moved into the driver.
Signed-off-by: Andrea Bastoni <[email protected]> --- configs/arm64/qemu-arm64.c | 4 +- configs/arm64/zynqmp-zcu102.c | 4 +- hypervisor/arch/arm64/Kbuild | 4 - hypervisor/arch/arm64/cache_layout.c | 148 ------------------ .../arch/arm64/include/asm/cache_layout.h | 21 --- hypervisor/arch/arm64/include/asm/coloring.h | 8 - 6 files changed, 2 insertions(+), 187 deletions(-) delete mode 100644 hypervisor/arch/arm64/cache_layout.c delete mode 100644 hypervisor/arch/arm64/include/asm/cache_layout.h diff --git a/configs/arm64/qemu-arm64.c b/configs/arm64/qemu-arm64.c index f064c1b0..ff4bcb25 100644 --- a/configs/arm64/qemu-arm64.c +++ b/configs/arm64/qemu-arm64.c @@ -45,9 +45,7 @@ struct { .pci_is_virtual = 1, .pci_domain = 1, .color = { - /* in debug mode, the way_size is autodetected - * if it is not specified */ - /* .way_size = 0x20000, */ + .way_size = 0x20000, .root_map_offset = 0x0C000000000, }, .arm = { diff --git a/configs/arm64/zynqmp-zcu102.c b/configs/arm64/zynqmp-zcu102.c index cdff3ef2..0d721e63 100644 --- a/configs/arm64/zynqmp-zcu102.c +++ b/configs/arm64/zynqmp-zcu102.c @@ -46,9 +46,7 @@ struct { .pci_is_virtual = 1, .pci_domain = -1, .color = { - /* in debug mode, the way_size is autodetected - * if it is not specified */ - /* .way_size = 0x10000, */ + .way_size = 0x10000, .root_map_offset = 0x0C000000000, }, .iommu_units = { diff --git a/hypervisor/arch/arm64/Kbuild b/hypervisor/arch/arm64/Kbuild index c0705f12..a5525811 100644 --- a/hypervisor/arch/arm64/Kbuild +++ b/hypervisor/arch/arm64/Kbuild @@ -24,7 +24,3 @@ lib-y += entry.o setup.o control.o mmio.o paging.o caches.o traps.o lib-y += iommu.o smmu-v3.o ti-pvu.o lib-y += smmu.o lib-y += coloring.o - -ifdef CONFIG_DEBUG -lib-y += cache_layout.o -endif diff --git a/hypervisor/arch/arm64/cache_layout.c b/hypervisor/arch/arm64/cache_layout.c deleted file mode 100644 index 0f28a440..00000000 --- a/hypervisor/arch/arm64/cache_layout.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Jailhouse Cache Coloring Support - * - * Copyright (C) Università di Modena e Reggio Emilia, 2018 - * Copyright (C) Boston University, 2020 - * Copyright (C) Technical University of Munich, 2020 - * - * Authors: - * Luca Miccio <[email protected]> - * Renato Mancuso (BU) <[email protected]> - * Andrea Bastoni <[email protected]> - * - * Autodetection of the cache geometry. - * - * This work is licensed under the terms of the GNU GPL, version 2. See the - * COPYING file in the top-level directory. - */ - -#include <jailhouse/printk.h> -#include <jailhouse/utils.h> -#include <jailhouse/paging.h> -#include <asm/cache_layout.h> -#include <asm/sysregs.h> - -#define verb_print(fmt, ...) \ - printk("[COL] " fmt, ##__VA_ARGS__) - -#define MAX_CACHE_LEVEL 7 - -#define CLIDR_CTYPE(reg, n) GET_FIELD((reg), 3*(n)+2, 3*(n)) -#define CLIDR_ICB(reg) GET_FIELD((reg), 32, 30) - -enum clidr_ctype { - CLIDR_CTYPE_NOCACHE, - CLIDR_CTYPE_IONLY, - CLIDR_CTYPE_DONLY, - CLIDR_CTYPE_IDSPLIT, - CLIDR_CTYPE_UNIFIED, -}; - -#define CSSELR_LEVEL(reg) SET_FIELD((reg), 3, 1) -#define CSSELR_IND 0x1 - -/* Assume ARM v8.0, v8.1, v8.2 */ -#define CCSIDR_LINE_SIZE(reg) GET_FIELD((reg), 2, 0) -#define CCSIDR_ASSOC(reg) GET_FIELD((reg), 12, 3) -#define CCSIDR_NUM_SETS(reg) GET_FIELD((reg), 27, 13) - -const char * cache_types[] = {"Not present", "Instr. Only", "Data Only", "I+D Split", "Unified"}; - -typedef struct cache { - /* Total size of the cache in bytes */ - u64 size; - /* Size of a single way in bytes */ - u64 line_size; - /* Size of each cache line in bytes */ - u64 way_size; - /* Associativity */ - u32 assoc; - /* Max number of colors supported by this cache */ - u64 colors; - /* Which level is this cache at */ - int level; -} cache_t; - -/** Autodetect cache(s) geometry. - * Return the size of a way or 0 if no cache was detected. - */ -u64 arm_cache_layout_detect(void) -{ - /* First, parse CLIDR_EL1 to understand how many levels are - * present in the system. */ - u64 reg, geom; - unsigned int max_cache_level; - - unsigned int n; - cache_t cache; - u64 type, assoc, ls, sets; - - arm_read_sysreg(clidr_el1, reg); - - max_cache_level = CLIDR_ICB(reg); - if (max_cache_level == 0) { - max_cache_level = MAX_CACHE_LEVEL; - verb_print("\tUsing default max cache levels\n"); - } - verb_print("\tmax cache level = %u\n", max_cache_level); - - cache.way_size = 0; - cache.level = -1; - - for (n = 0; n < max_cache_level; ++n) { - type = CLIDR_CTYPE(reg, n); - verb_print("\tL%d Cache Type: %s\n", n + 1, cache_types[type]); - - if (type == CLIDR_CTYPE_NOCACHE) - continue; - - /* Fetch additional info about this cache level */ - arm_write_sysreg(csselr_el1, CSSELR_LEVEL(n)); - arm_read_sysreg(ccsidr_el1, geom); - - /* Parse info about this level */ - ls = 1 << (4 + CCSIDR_LINE_SIZE(geom)); - assoc = CCSIDR_ASSOC(geom) + 1; - sets = CCSIDR_NUM_SETS(geom) + 1; - - verb_print("\t\tTotal size: %lld\n", ls * assoc * sets); - verb_print("\t\tLine size: %lld\n", ls); - verb_print("\t\tAssoc.: %lld\n", assoc); - verb_print("\t\tNum. sets: %lld\n", sets); - - if (type == CLIDR_CTYPE_IDSPLIT) { - arm_write_sysreg(csselr_el1, (CSSELR_LEVEL(n) | CSSELR_IND)); - arm_read_sysreg(ccsidr_el1, geom); - - ls = 1 << (4 + CCSIDR_LINE_SIZE(geom)); - assoc = CCSIDR_ASSOC(geom) + 1; - sets = CCSIDR_NUM_SETS(geom) + 1; - - verb_print("\t\tTotal size (I): %lld\n", ls * assoc * sets); - verb_print("\t\tLine size (I): %lld\n", ls); - verb_print("\t\tAssoc. (I): %lld\n", assoc); - verb_print("\t\tNum. sets (I): %lld\n", sets); - - } - - /* Perform coloring at the last unified cache level */ - if (type == CLIDR_CTYPE_UNIFIED) { - cache.level = n + 1; - - cache.size = ls * assoc * sets; - cache.line_size = ls; - cache.way_size = ls * sets; - cache.assoc = assoc; - cache.colors = sets / (PAGE_SIZE / ls); - - /* Compute the max. number of colors */ - verb_print("\t\tNum. colors: %lld\n", cache.colors); - } - - } - - verb_print("\tNOTE: L%d Cache selected for coloring.\n", cache.level); - - return cache.way_size; -} - diff --git a/hypervisor/arch/arm64/include/asm/cache_layout.h b/hypervisor/arch/arm64/include/asm/cache_layout.h deleted file mode 100644 index aad4339d..00000000 --- a/hypervisor/arch/arm64/include/asm/cache_layout.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Jailhouse Cache Coloring Support - * - * Copyright (C) Università di Modena e Reggio Emilia, 2018 - * Copyright (C) Boston University, 2020 - * Copyright (C) Technical University of Munich, 2020 - * - * Authors: - * Luca Miccio <[email protected]> - * Renato Mancuso (BU) <[email protected]> - * Andrea Bastoni <[email protected]> - * - * This work is licensed under the terms of the GNU GPL, version 2. See the - * COPYING file in the top-level directory. - */ -#ifdef CONFIG_DEBUG -/** Autodetect cache(s) geometry. - * Return the size of a way or 0 if no cache was detected. - */ -extern u64 arm_cache_layout_detect(void); -#endif diff --git a/hypervisor/arch/arm64/include/asm/coloring.h b/hypervisor/arch/arm64/include/asm/coloring.h index b2911a4b..9cb50889 100644 --- a/hypervisor/arch/arm64/include/asm/coloring.h +++ b/hypervisor/arch/arm64/include/asm/coloring.h @@ -22,7 +22,6 @@ #include <jailhouse/control.h> #include <jailhouse/assert.h> #include <jailhouse/panic.h> -#include <asm/cache_layout.h> #ifdef CONFIG_DEBUG #define col_print(fmt, ...) \ @@ -73,13 +72,6 @@ static inline void arm_color_dcache_flush_memory_region( static inline void arm_color_init(void) { coloring_way_size = system_config->platform_info.color.way_size; -#ifdef CONFIG_DEBUG - if (coloring_way_size == 0) { - coloring_way_size = arm_cache_layout_detect(); - } -#endif - coloring_root_map_offset = - system_config->platform_info.color.root_map_offset; printk("Init Coloring: Way size: 0x%llx, TMP load addr: 0x%llx\n", coloring_way_size, coloring_root_map_offset); -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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