The variable cbm_max captures the position of the most significant bit
of the CBM, rather than the number of bits in the CBM. This should be
considered when checking non-root cell configurations to be valid,
otherwise the non-root cells can never access the top-most bit in the
CBM.
This off-by-one error ensured that the ROOT_COS CBM always had at least
one private bit in the CBM, preventing it from becoming empty. However,
empty ROOT_COS CBMs are well accounted for in the code.
Fixes: 3f04eb1753bb ("x86: Introduce Cache Allocation Technology support
for Intel CPUs")
Signed-off-by: Bram Hooimeijer <[email protected]>
---
hypervisor/arch/x86/cat.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hypervisor/arch/x86/cat.c b/hypervisor/arch/x86/cat.c
index d3425f7b..f4c6f5d6 100644
--- a/hypervisor/arch/x86/cat.c
+++ b/hypervisor/arch/x86/cat.c
@@ -173,7 +173,8 @@ static int cat_cell_init(struct cell *cell)
if (cell->config->num_cache_regions != 1 ||
cache->type != JAILHOUSE_CACHE_L3 ||
- cache->size == 0 || (cache->start + cache->size) > cbm_max)
+ cache->size == 0 ||
+ (cache->start + cache->size - 1) > cbm_max)
return trace_error(-EINVAL);
cell->arch.cat_mask =
--
2.28.0
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