On 23/03/2021, Jan Kiszka <[email protected]> wrote: > On 23.03.21 16:36, Angelo Ruocco wrote: >> On 23/03/2021, Jan Kiszka <[email protected]> wrote: >>> On 23.03.21 12:33, Angelo Ruocco wrote: >>>> On 23/03/2021, Jan Kiszka <[email protected]> wrote: >>>>> On 23.03.21 11:17, Angelo Ruocco wrote: >>>>>> Hi Jan, all, >>>>>> >>>>>> I have seen that arm-zero-exits has been merged into next. >>>>>> >>>>>> My understanding is that right now the only officially supported >>>>>> boards, meaning supporting both jailhouse and SDEI, are NXP's ones, >>>>>> with only a experimental patch for the xilinx zynqmp firmware to >>>>>> enable SDEI. >>>>>> >>>>>> Regarding that patch, I have looked at it, tested it and added the >>>>>> missing non-secure-boundary check. >>>>>> >>>>>> Are you thinking of submitting it upstream? If so, how do you want to >>>>>> proceed? >>>>> >>>>> If you have everything ready with the patch, I would not mind if you >>>>> pushed that upstream. Just CC me. >>>> >>>> The only thing missing is a proper commit message, I could also write >>>> that, but I don't really know whether it's appropriate for me to >>>> submit a patch of which I don't have the authorship. What do you >>>> think? >>> >>> But you added something to it as you wrote above, no? >> >> Yes, but that's hardly worth adding my signature to the patch, not to >> mention authorship. >> >>> Otherwise, share what you have, and I will kick off the gerrit mess. >> >> That is ok by me. How do you want me to send the patch? Here in the >> mailing list? >> > > Yes, just drop it here, attached or inline. > > Jan > > -- > Siemens AG, T RDA IOT > Corporate Competence Center Embedded Linux >
You'll find the patch attached. Thanks, Angelo -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/CADiTV-2pfQ4SVayR2A_3%2BogF7T743RjM%2BW7R0hQFNu%3DNG5c5wA%40mail.gmail.com.
From e7abca4ef270573023eb072d368e203c6933563a Mon Sep 17 00:00:00 2001 From: Jan Kiszka <[email protected]> Date: Tue, 14 Jul 2020 22:36:59 +0200 Subject: [PATCH] zynqmp: Add SDEI support Signed-off-by: Jan Kiszka <[email protected]> Signed-off-by: Angelo Ruocco <[email protected]> --- plat/xilinx/zynqmp/include/platform_def.h | 27 ++++++++++---- plat/xilinx/zynqmp/platform.mk | 5 +++ plat/xilinx/zynqmp/zynqmp_ehf.c | 26 ++++++++++++++ plat/xilinx/zynqmp/zynqmp_sdei.c | 43 +++++++++++++++++++++++ 4 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 plat/xilinx/zynqmp/zynqmp_ehf.c create mode 100644 plat/xilinx/zynqmp/zynqmp_sdei.c diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index 27968409e..ad65e9539 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -36,8 +36,8 @@ * little space for growth. */ #ifndef ZYNQMP_ATF_MEM_BASE -#if !DEBUG && defined(SPD_none) -# define BL31_BASE 0xfffea000 +#if !DEBUG && defined(SPD_none) && !defined(SDEI_SUPPORT) +# define BL31_BASE 0xfffe7000 # define BL31_LIMIT 0xffffffff #else # define BL31_BASE 0x1000 @@ -91,6 +91,21 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) +/* Platform macros to support exception handling framework */ +#define PLAT_PRI_BITS U(3) +#define PLAT_SDEI_CRITICAL_PRI 0x10 +#define PLAT_SDEI_NORMAL_PRI 0x20 + +/* SDEI dynamic private event numbers */ +#define ZYNQMP_SDEI_DP_EVENT_0 U(100) +#define ZYNQMP_SDEI_DP_EVENT_1 U(101) +#define ZYNQMP_SDEI_DP_EVENT_2 U(102) + +/* SDEI dynamic shared event numbers */ +#define ZYNQMP_SDEI_DS_EVENT_0 U(200) +#define ZYNQMP_SDEI_DS_EVENT_1 U(201) +#define ZYNQMP_SDEI_DS_EVENT_2 U(202) + #define PLAT_ARM_GICD_BASE BASE_GICD_BASE #define PLAT_ARM_GICC_BASE BASE_GICC_BASE /* @@ -102,8 +117,6 @@ #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -124,8 +137,6 @@ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE), \ - INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_EDGE), \ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -142,6 +153,8 @@ GIC_INTR_CFG_EDGE) #endif -#define PLAT_ARM_G0_IRQ_PROPS(grp) +#define PLAT_ARM_G0_IRQ_PROPS(grp) \ + INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ + GIC_INTR_CFG_EDGE) #endif /* PLATFORM_DEF_H */ diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk index 6e700b9b1..0d0745226 100644 --- a/plat/xilinx/zynqmp/platform.mk +++ b/plat/xilinx/zynqmp/platform.mk @@ -14,6 +14,9 @@ override RESET_TO_BL31 := 1 override GICV2_G0_FOR_EL3 := 1 override WARMBOOT_ENABLE_DCACHE_EARLY := 1 +EL3_EXCEPTION_HANDLING := 1 +SDEI_SUPPORT := 1 + # Do not enable SVE ENABLE_SVE_FOR_NS := 0 @@ -90,6 +93,8 @@ BL31_SOURCES += drivers/arm/cci/cci.c \ plat/xilinx/zynqmp/plat_zynqmp.c \ plat/xilinx/zynqmp/plat_topology.c \ plat/xilinx/zynqmp/sip_svc_setup.c \ + plat/xilinx/zynqmp/zynqmp_ehf.c \ + plat/xilinx/zynqmp/zynqmp_sdei.c \ plat/xilinx/zynqmp/pm_service/pm_svc_main.c \ plat/xilinx/zynqmp/pm_service/pm_api_sys.c \ plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c \ diff --git a/plat/xilinx/zynqmp/zynqmp_ehf.c b/plat/xilinx/zynqmp/zynqmp_ehf.c new file mode 100644 index 000000000..cce01e5cd --- /dev/null +++ b/plat/xilinx/zynqmp/zynqmp_ehf.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) Siemens AG, 2020 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <bl31/ehf.h> + +/* + * Enumeration of priority levels on ARM platforms. + */ +ehf_pri_desc_t zynqmp_exceptions[] = { +#if SDEI_SUPPORT + /* Critical priority SDEI */ + EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI), + + /* Normal priority SDEI */ + EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI), +#endif +}; + +/* Plug in ARM exceptions to Exception Handling Framework. */ +EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS); diff --git a/plat/xilinx/zynqmp/zynqmp_sdei.c b/plat/xilinx/zynqmp/zynqmp_sdei.c new file mode 100644 index 000000000..2753496a0 --- /dev/null +++ b/plat/xilinx/zynqmp/zynqmp_sdei.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) Siemens AG, 2020 + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* SDEI configuration for ARM platforms */ + +#include <bl31/ehf.h> +#include <common/debug.h> +#include <services/sdei.h> + +#include <plat/common/platform.h> +#include <platform_def.h> + +int arm_validate_ns_entrypoint(uintptr_t entrypoint) +{ + return (entrypoint < BL31_BASE) || (entrypoint > BL31_LIMIT) ? 0 : -1; +} + +/* Private event mappings */ +static sdei_ev_map_t zynqmp_sdei_private[] = { + SDEI_DEFINE_EVENT_0(8), + SDEI_PRIVATE_EVENT(ZYNQMP_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), + SDEI_PRIVATE_EVENT(ZYNQMP_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), + SDEI_PRIVATE_EVENT(ZYNQMP_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), +}; + +/* Shared event mappings */ +static sdei_ev_map_t zynqmp_sdei_shared[] = { + SDEI_SHARED_EVENT(ZYNQMP_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), + SDEI_SHARED_EVENT(ZYNQMP_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), + SDEI_SHARED_EVENT(ZYNQMP_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), +}; + +void plat_sdei_setup(void) +{ + INFO("SDEI platform setup\n"); +} + +/* Export ARM SDEI events */ +REGISTER_SDEI_MAP(zynqmp_sdei_private, zynqmp_sdei_shared); -- 2.17.1
