> Subject: Re: [PATCH 1/5] arm: gic-v3: inject irq priority to inmates
> 
> On 23.03.21 07:25, [email protected] wrote:
> > From: Peng Fan <[email protected]>
> >
> > Inject physical IRQ priority to inmates.
> >
> 
> Reasoning is missing, use case description. Specifically as this approach has 
> no
> influence on the ordering in the software queue. And as it's only targeting
> GICv2. And possibly there are more limitations.

Before this fix, any cell was receiving all interrupts at the highest level 
(priority=0),
so the inmate code was not able to mask sources or to enable priority-based ISR
preemption/nesting.

This version patch not take PPI into consideration, I may need to add that in 
v2.

Thanks,
Peng.

> 
> So far the decision was to ignore those rarely used IRQ prios because of the
> additional complexity to emulate them accurately.
> 
> See also
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Fsiemens%2Fjailhouse%2Fcommit%2F03475882880dc5ae49d0852c62
> 8a8b8958be80ac&amp;data=04%7C01%7Cpeng.fan%40nxp.com%7C399011
> 156dea40beabae08d8edcfbfb9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7
> C0%7C0%7C637520823814036005%7CUnknown%7CTWFpbGZsb3d8eyJWIjoi
> MC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C10
> 00&amp;sdata=KWf9Mblg3KywaIl04YRpuFTCE6S3fzRrJXnDC5gKZqc%3D&am
> p;reserved=0.
> 
> > Signed-off-by: Peng Fan <[email protected]>
> > ---
> >  hypervisor/arch/arm-common/gic-v3.c | 12 ++++++++++++
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/hypervisor/arch/arm-common/gic-v3.c
> > b/hypervisor/arch/arm-common/gic-v3.c
> > index 4ebb2357..2293f844 100644
> > --- a/hypervisor/arch/arm-common/gic-v3.c
> > +++ b/hypervisor/arch/arm-common/gic-v3.c
> > @@ -533,9 +533,11 @@ static void gicv3_eoi_irq(u32 irq_id, bool
> > deactivate)
> >
> >  static int gicv3_inject_irq(u16 irq_id, u16 sender)  {
> > +   void *gicr = this_cpu_public()->gicr.base + GICR_SGI_BASE;
> >     unsigned int n;
> >     int free_lr = -1;
> >     u32 elsr;
> > +   u32 iprio;
> >     u64 lr;
> >
> >     arm_read_sysreg(ICH_ELSR_EL2, elsr); @@ -572,6 +574,16 @@ static
> int
> > gicv3_inject_irq(u16 irq_id, u16 sender)
> >     if (!is_sgi(irq_id)) {
> >             lr |= ICH_LR_HW_BIT;
> >             lr |= (u64)irq_id << ICH_LR_PHYS_ID_SHIFT;
> > +
> > +           if (is_spi(irq_id))
> > +                   iprio = mmio_read32(gicd_base + GICD_IPRIORITYR +
> > +                                       (irq_id & ~3));
> > +           else
> > +                   iprio = mmio_read32(gicr + GICR_IPRIORITYR +
> > +                                       (irq_id & ~3));
> > +
> > +           iprio = (iprio >> ((irq_id & 3) * 8)) & 0xff;
> > +           lr |= (u64)iprio << ICH_LR_PRIORITY_SHIFT;
> >     }
> >     /* GICv3 doesn't support the injection of the calling CPU ID */
> >
> >
> 
> Jan
> 
> --
> Siemens AG, T RDA IOT
> Corporate Competence Center Embedded Linux

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