On 03.06.21 17:27, Dongjiu Geng wrote:
> The register offset and bits offset should follow below rules.
> 1. The corresponding GICD_SPENDSGIR register number n, is given by n = x DIV 4
> 2. The offset of the required GICD_SPENDSGIR is (0xF20 + (4*n))
> 3. The SGI Set-pending field offset y, is given by y = x MOD 4
>
> Signed-off-by: Dongjiu Geng <[email protected]>
> ---
> hypervisor/arch/arm-common/gic-v2.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hypervisor/arch/arm-common/gic-v2.c
> b/hypervisor/arch/arm-common/gic-v2.c
> index 31371de9..03b91fa1 100644
> --- a/hypervisor/arch/arm-common/gic-v2.c
> +++ b/hypervisor/arch/arm-common/gic-v2.c
> @@ -364,13 +364,20 @@ static int gicv2_get_pending_irq(void)
>
> static void gicv2_inject_phys_irq(u16 irq_id)
> {
> - unsigned int offset = (irq_id / 32) * 4;
> + unsigned int offset;
> unsigned int mask = 1 << (irq_id % 32);
>
> if (is_sgi(irq_id)) {
> + /*
> + * The offset of the required GICD_SPENDSGIR is (0xF20 + (4*n)),
> + * n is given by irq_id DIV 4, the SGI Set-pending field offset
> + * is given by irq_id MOD 4.
> + */
> + offset = (irq_id / 4) * 4 + irq_id % 4;
> /* Inject with CPU 0 as source - we don't track the origin. */
> mmio_write8(gicd_base + GICD_SPENDSGIR + irq_id, 1);
I cannot follow yet: Neither now nor with your patch applied offset (as
well as mask) is used if we take this branch.
Are you seeing a problem in reality with the current code? Can you
describe how to reproduce that scenario?
Thanks,
Jan
> } else {
> + offset = (irq_id / 32) * 4;
> /*
> * Hardware interrupts are physically active until they are
> * processed by the cell. Deactivate them first so that we can
>
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