On 03.06.21 12:02, along li wrote: > So this means: jailhouse cann't partition a PCI device into > inmate on raspberry 4 board for now? > If we want to partition a PCI device into inmate, we should modify > the source code. Is this right? >
Jailhouse partitions at a low abstraction level. It can split what the hardware permits to split. On a common ARM SoC, those are generally platform devices - which can include complete PCI host controllers with all devices behind it. PCI buses can be split as well, provided the hardware is able to tell PCI devices apart when DMA requests come in - or you have no IOMMU anyway and, thus, cannot completely isolate devices in the first place (like on the RPi4). So, assuming you are not looking for secure isolation and a fine with best-effort, the next challenge with PCI partitioning is managing the host controller. We successfully partitioned in the past devices on the Seattle AMD SoC which contained a generic-type PCI controller. I didn't study the broadcom PCIe controller interface yet, but I bet a bit of adjustment will be needed, primarily around intercepting, interpreting and executing PCI config accesses and managing MSIs programmed by the guest. If you are looking for secure isolation, choose a SoC with IOMMU (SMMU) support. Jan -- Siemens AG, T RDA IOT Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/db85b6dc-4d10-3e91-cf4b-4ea6d8e44b2d%40siemens.com.
