On 02.02.21 17:44, Bram Hooimeijer wrote:
> Upon cell creation, check whether there exists a cell with an identical
> mask as should be created now. In that case, reuse that cell's COS, to
> increase the number of available COS's.
>
> Recent Intel Xeon Processors, which have CAT support, can have up to 28
> cores. This might exceed the number of COSes available, as this
> typically relates to the number of cache ways rather than the number of
> cores on the processor. Therefore, creating a cell per core which is
> isolated from the root becomes impossible if each core requires a
> private COS.
>
> Signed-off-by: Bram Hooimeijer <[email protected]>
> ---
> hypervisor/arch/x86/cat.c | 28 ++++++++++++++++++----------
> 1 file changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/hypervisor/arch/x86/cat.c b/hypervisor/arch/x86/cat.c
> index c91560a2..fc943a0d 100644
> --- a/hypervisor/arch/x86/cat.c
> +++ b/hypervisor/arch/x86/cat.c
> @@ -45,14 +45,22 @@ static void cat_update_cell(struct cell *cell)
> public_per_cpu(cpu)->update_cat = true;
> }
>
> -static u32 get_free_cos(void)
> +static u32 get_suitable_cos(struct cell *cell)
> {
> - struct cell *cell;
> + struct cell *other_cell;
> u32 cos = 0;
>
> + /* Check whether a COS can be reused.
> + *
> + * Never reuse the ROOT_COS, as the corresponding CBM can be changed
> + * when new cells are made, collaterally impacting the created cell. */
> + for_each_non_root_cell(other_cell)
> + if (cell->arch.cat_mask == other_cell->arch.cat_mask)
> + return other_cell->arch.cos;
> +
> retry:
> - for_each_cell(cell)
> - if (cell->arch.cos == cos) {
> + for_each_cell(other_cell)
> + if (other_cell->arch.cos == cos) {
> cos++;
> goto retry;
> }
> @@ -166,12 +174,6 @@ static int cat_cell_init(struct cell *cell)
> return 0;
>
> if (cell->config->num_cache_regions > 0) {
> - if (cell != &root_cell) {
> - cell->arch.cos = get_free_cos();
> - if (cell->arch.cos > (u32)cos_max)
> - return trace_error(-EBUSY);
> - }
> -
> cache = jailhouse_cell_cache_regions(cell->config);
>
> if (cell->config->num_cache_regions != 1 ||
> @@ -183,6 +185,12 @@ static int cat_cell_init(struct cell *cell)
> cell->arch.cat_mask =
> BIT_MASK(cache->start + cache->size - 1, cache->start);
>
> + if (cell != &root_cell) {
> + cell->arch.cos = get_suitable_cos(cell);
> + if (cell->arch.cos > (u32)cos_max)
> + return trace_error(-EBUSY);
> + }
> +
> if (cell != &root_cell &&
> !(cache->flags & JAILHOUSE_CACHE_ROOTSHARED) &&
> (root_cell.arch.cat_mask & cell->arch.cat_mask) != 0)
>
OK, I suppose this patch needs patch 2, right?
I wonder if we cannot achieve this via offline configuration as well.
These are the new config data structures I plan to introduce:
/* cache types */
#define JAILHOUSE_CACHE_L2 0x00
#define JAILHOUSE_CACHE_L3 0x01
/* cache flags */
#define JAILHOUSE_CACHE_ROOTSHARED 0x01
#define JAILHOUSE_CACHE_CODE_ONLY 0x02
#define JAILHOUSE_CACHE_DATA_ONLY 0x04
struct jailhouse_cache {
__u32 start;
__u32 size;
__u16 id;
__u8 type;
__u8 flags;
} __attribute__((packed));
#define JAILHOUSE_MAX_CPU_CACHE_REGIONS 4
struct jailhouse_cpu {
__u64 phys_id;
__u16 cache_regions[JAILHOUSE_MAX_CPU_CACHE_REGIONS];
} __attribute__((packed));
cache_regions will refer to jailhouse_cache entries by their 'id'. Maybe
we can also derive the COS ID from that. But this isn't fully thought
through yet, specifically regarding the scenario of both L2 and L3 cache
configurations (not sure if such CPUs already exists).
I'm not a fan of too much logic in the hypervisor if allocation could
already be done upfront.
Jan
--
Siemens AG, T RDA IOT
Corporate Competence Center Embedded Linux
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