Dear Jailhouse community,
We are currently running into an issue when using PCIe caps beyond 0x100, e.g.
those in the extended config space.
We want to write to some address, say 0x480. We assign the PCI cap to the
non-root cell as shown below.
> .pci_devices = {
> /* PCIDevice: 3b:00.0 */
> {
> .type = JAILHOUSE_PCI_TYPE_DEVICE,
> .iommu = 5,
> .domain = 0x0,
> .bdf = 0x3b00,
> .bar_mask = {
> 0xff000000, 0xffffffff, 0xff000000,
> 0xffffffff, 0x00000000, 0x00000000,
> },
> .caps_start = 0,
> .num_caps = 1,
> .num_msi_vectors = 0,
> .msi_64bits = 0,
> .msi_maskable = 0,
> .num_msix_vectors = 0,
> .msix_region_size = 0x0,
> .msix_address = 0x0,
> },
> },
> .pci_caps = {
> {
> .id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
> .start = 0x480,
> .len = 0x80,
> .flags = JAILHOUSE_PCICAPS_WRITE
> },
> },
If we now write to this address, we get:
> FATAL: Invalid PCI config write, port: 0xcfc, size: 4, address port:
> 0x843b0080
Even though the address port looks correct. Diving into the hypervisor, the
value of address in hypervisor/pci.c:pci_cfg_write_moderate is 0x80 instead of
0x480. Due to that, it cannot find the cap.
The same happens for reads, however, with no cap these are still performed
apparently.
The wrong address seems to originate from
hypervisor/arch/x86/pci.c:x86_pci_config_handler, which has the following
snippet:
address = (addr_port_val & PCI_ADDR_REGNUM_MASK) + port
- PCI_REG_DATA_PORT;
The extended config space, ie bits [31:24] from addr_port_val are dropped here.
Hence, no config access can be done from 0x100 onwards.
I think this should be:
address = (addr_port_val & PCI_ADDR_REGNUM_MASK) + port
- PCI_REG_DATA_PORT
+ ((addr_port_val && BITMASK(31,24))>>16);
Is this a bug, or is this intentional and did I misconfigure the PCI extended
capabilities? I can happily submit a patch, but given that PCIe usage is so
common, I expect I have misconfigured something.
Best regards,
Bram Hooimeijer
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