Thanks! The cause of the bug is that the MMIO address is not page aligned！
在2021年12月21日星期二 UTC+8 21:06:51<Bezdeka, Florian> 写道： > On Tue, 2021-12-21 at 04:45 -0800, jiajun huang wrote: > > > > Initializing Jailhouse hypervisor v0.12 (294-g6af5edf-dirty) on CPU 5 > > Code location: 0xfffffffff0000050 > > Using x2APIC > > Page pool usage after early setup: mem 134/32207, remap 0/131072 > > Initializing processors: > > CPU 5... (APIC ID 34) OK > > CPU 1... (APIC ID 2) OK > > CPU 3... (APIC ID 6) OK > > CPU 0... (APIC ID 0) OK > > CPU 6... (APIC ID 36) OK > > CPU 2... (APIC ID 4) OK > > CPU 7... (APIC ID 38) OK > > CPU 4... (APIC ID 32) OK > > Initializing unit: VT-d > > DMAR unit @0xfbffe000/0x1000 > > DMAR unit @0xdfffc000/0x1000 > > Reserving 24 interrupt(s) for device 00:1f.7 at index 0 > > Reserving 24 interrupt(s) for device 00:05.4 at index 24 > > Reserving 24 interrupt(s) for device 80:05.4 at index 48 > > Initializing unit: IOAPIC > > Initializing unit: Cache Allocation Technology > > Initializing unit: PCI > > Adding PCI device 00:00.0 to cell "RootCell" > > Adding virtual PCI device 00:17.0 to cell "RootCell" > > Adding virtual PCI device 00:18.0 to cell "RootCell" > > Adding PCI device 00:01.0 to cell "RootCell" > > Reserving 2 interrupt(s) for device 00:01.0 at index 72 > > Adding PCI device 00:01.1 to cell "RootCell" > > Reserving 2 interrupt(s) for device 00:01.1 at index 74 > > Adding PCI device 00:03.0 to cell "RootCell" > > Reserving 2 interrupt(s) for device 00:03.0 at index 76 > > Adding PCI device 00:03.2 to cell "RootCell" > > Reserving 2 interrupt(s) for device 00:03.2 at index 78 > > Adding PCI device 00:05.0 to cell "RootCell" > > Adding PCI device 00:05.2 to cell "RootCell" > > Adding PCI device 00:05.4 to cell "RootCell" > > Adding PCI device 00:11.0 to cell "RootCell" > > Reserving 1 interrupt(s) for device 00:11.0 at index 80 > > Adding PCI device 00:1a.0 to cell "RootCell" > > Adding PCI device 00:1c.0 to cell "RootCell" > > Reserving 1 interrupt(s) for device 00:1c.0 at index 81 > > Adding PCI device 00:1c.1 to cell "RootCell" > > Reserving 1 interrupt(s) for device 00:1c.1 at index 82 > > Adding PCI device 00:1c.3 to cell "RootCell" > > Reserving 1 interrupt(s) for device 00:1c.3 at index 83 > > Adding PCI device 00:1d.0 to cell "RootCell" > > Adding PCI device 00:1e.0 to cell "RootCell" > > Adding PCI device 00:1f.0 to cell "RootCell" > > Adding PCI device 00:1f.2 to cell "RootCell" > > Reserving 1 interrupt(s) for device 00:1f.2 at index 84 > > Adding PCI device 00:1f.3 to cell "RootCell" > > Adding PCI device 06:00.0 to cell "RootCell" > > Reserving 5 interrupt(s) for device 06:00.0 at index 85 > > Adding PCI device 07:00.0 to cell "RootCell" > > Reserving 5 interrupt(s) for device 07:00.0 at index 90 > > Adding PCI device 08:00.0 to cell "RootCell" > > Reserving 1 interrupt(s) for device 08:00.0 at index 95 > > Adding PCI device 09:00.0 to cell "RootCell" > > Adding PCI device 7f:08.0 to cell "RootCell" > > Adding PCI device 7f:09.0 to cell "RootCell" > > Adding PCI device 7f:0a.0 to cell "RootCell" > > Adding PCI device 7f:0a.1 to cell "RootCell" > > Adding PCI device 7f:0a.2 to cell "RootCell" > > Adding PCI device 7f:0a.3 to cell "RootCell" > > Adding PCI device 7f:0b.0 to cell "RootCell" > > Adding PCI device 7f:0b.3 to cell "RootCell" > > Adding PCI device 7f:0c.0 to cell "RootCell" > > Adding PCI device 7f:0c.1 to cell "RootCell" > > Adding PCI device 7f:0d.0 to cell "RootCell" > > Adding PCI device 7f:0d.1 to cell "RootCell" > > Adding PCI device 7f:0e.0 to cell "RootCell" > > Adding PCI device 7f:0e.1 to cell "RootCell" > > Adding PCI device 7f:0f.0 to cell "RootCell" > > Adding PCI device 7f:0f.1 to cell "RootCell" > > Adding PCI device 7f:0f.2 to cell "RootCell" > > Adding PCI device 7f:0f.3 to cell "RootCell" > > Adding PCI device 7f:0f.4 to cell "RootCell" > > Adding PCI device 7f:0f.5 to cell "RootCell" > > Adding PCI device 7f:10.0 to cell "RootCell" > > Adding PCI device 7f:10.1 to cell "RootCell" > > Adding PCI device 7f:10.2 to cell "RootCell" > > Adding PCI device 7f:10.3 to cell "RootCell" > > Adding PCI device 7f:10.4 to cell "RootCell" > > Adding PCI device 7f:10.5 to cell "RootCell" > > Adding PCI device 7f:10.6 to cell "RootCell" > > Adding PCI device 7f:10.7 to cell "RootCell" > > Adding PCI device 7f:13.0 to cell "RootCell" > > Adding PCI device 7f:13.1 to cell "RootCell" > > Adding PCI device 7f:13.4 to cell "RootCell" > > Adding PCI device 7f:13.5 to cell "RootCell" > > Adding PCI device 7f:16.0 to cell "RootCell" > > Adding PCI device 7f:16.1 to cell "RootCell" > > Adding PCI device 7f:16.2 to cell "RootCell" > > Adding PCI device 80:03.0 to cell "RootCell" > > Reserving 2 interrupt(s) for device 80:03.0 at index 96 > > Adding PCI device 80:03.2 to cell "RootCell" > > Reserving 2 interrupt(s) for device 80:03.2 at index 98 > > Adding PCI device 80:05.0 to cell "RootCell" > > Adding PCI device 80:05.2 to cell "RootCell" > > Adding PCI device 80:05.4 to cell "RootCell" > > Adding PCI device ff:08.0 to cell "RootCell" > > Adding PCI device ff:09.0 to cell "RootCell" > > Adding PCI device ff:0a.0 to cell "RootCell" > > Adding PCI device ff:0a.1 to cell "RootCell" > > Adding PCI device ff:0a.2 to cell "RootCell" > > Adding PCI device ff:0a.3 to cell "RootCell" > > Adding PCI device ff:0b.0 to cell "RootCell" > > Adding PCI device ff:0b.3 to cell "RootCell" > > Adding PCI device ff:0c.0 to cell "RootCell" > > Adding PCI device ff:0c.1 to cell "RootCell" > > Adding PCI device ff:0d.0 to cell "RootCell" > > Adding PCI device ff:0d.1 to cell "RootCell" > > Adding PCI device ff:0e.0 to cell "RootCell" > > Adding PCI device ff:0e.1 to cell "RootCell" > > Adding PCI device ff:0f.0 to cell "RootCell" > > Adding PCI device ff:0f.1 to cell "RootCell" > > Adding PCI device ff:0f.2 to cell "RootCell" > > Adding PCI device ff:0f.3 to cell "RootCell" > > Adding PCI device ff:0f.4 to cell "RootCell" > > Adding PCI device ff:0f.5 to cell "RootCell" > > Adding PCI device ff:10.0 to cell "RootCell" > > Adding PCI device ff:10.1 to cell "RootCell" > > Adding PCI device ff:10.2 to cell "RootCell" > > Adding PCI device ff:10.3 to cell "RootCell" > > Adding PCI device ff:10.4 to cell "RootCell" > > Adding PCI device ff:10.5 to cell "RootCell" > > Adding PCI device ff:10.6 to cell "RootCell" > > Adding PCI device ff:10.7 to cell "RootCell" > > Adding PCI device ff:13.0 to cell "RootCell" > > Adding PCI device ff:13.1 to cell "RootCell" > > Adding PCI device ff:13.4 to cell "RootCell" > > Adding PCI device ff:13.5 to cell "RootCell" > > Adding PCI device ff:16.0 to cell "RootCell" > > Adding PCI device ff:16.1 to cell "RootCell" > > Adding PCI device ff:16.2 to cell "RootCell" > > Page pool usage after late setup: mem 469/32207, remap 65549/131072 > > Activating hypervisor > > FATAL: unsupported instruction (0x83 0x00 0x00 0x00) > > FATAL: Invalid MMIO/RAM read, addr: 0x00000000538c1020 size: 0 > ^^ > +- First problem > > > RIP: 0xffffffff91ac0aff RSP: 0xffffa70e496c3af0 FLAGS: 10286 > > RAX: 0xffff8e13d38c1018 RBX: 0x00000000538c1018 RCX: > > 0x0000000000000000 > > RDX: 0x0000000000000001 RSI: 0x0000000000000040 RDI: > > 0xffff8e13d38c1018 > > CS: 10 BASE: 0x0000000000000000 AR-BYTES: a09b EFER.LMA 1 > > CR0: 0x0000000080050033 CR3: 0x000000105704a002 CR4: > > 0x00000000001626e0 > > EFER: 0x0000000000000d01 > > Parking CPU 7 (Cell: "RootCell") > > FATAL: unsupported instruction (0xf3 0x00 0x00 0x00) > > FATAL: Invalid MMIO/RAM write, addr: 0x000000006b7b4800 size: 0 > ^^ > +- Second problem > > Are those memory regions related to your IVSHMEM devices? If so make > sure that the root cell is allowed to read/write them. > > Normally those regions are located inside the hypervisor memory area > (memmap= on JH kernel cmdline) and mapped into both communication > partner cells using JAILHOUSE_SHMEM_NET_REGIONS() inside the > .mem_regions field of cell configurations. > > HTH, > Florian > > > RIP: 0xffffffff91c76ed6 RSP: 0xffffa70e4662f910 FLAGS: 10246 > > RAX: 0xffff8e13eb7b4800 RBX: 0x0000000000000106 RCX: > > 0x0000000000000008 > > RDX: 0x0000000000000008 RSI: 0xffff8e1bda209740 RDI: > > 0xffff8e13eb7b4800 > > CS: 10 BASE: 0x0000000000000000 AR-BYTES: a09b EFER.LMA 1 > > CR0: 0x0000000080050033 CR3: 0x00000008b7e0a001 CR4: > > 0x00000000001626e0 > > EFER: 0x0000000000000d01 > > Parking CPU 1 (Cell: "RootCell") > > > > > > 在2021年12月21日星期二 UTC+8 20:43:08<jiajun huang> 写道： > > > Hi everyone, > > > When I tried to add two ivshmem PCI devices to the root cell, a > > > "FATAL: unsupported instruction" bug occurred. This bug is caused > > > by x86_mmio_parse. How can I fix this bug? Below is my root-cell > > > configuration and log output from the port. > > > > > > thanks， > > > Jiajun > > -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/1e24e708-b133-4785-8f07-aad465f0d7ffn%40googlegroups.com.
