Add support for TI AM625 Starter Kit platform along with eMMC and non-eMMC
Linux inmate cell configurations.
Signed-off-by: Matt Ranostay <mranos...@ti.com>
---
configs/arm64/dts/inmate-k3-am625-sk-emmc.dts | 28 ++
configs/arm64/dts/inmate-k3-am625-sk.dts | 163 +++++++++
configs/arm64/k3-am625-inmate-demo.c | 72 ++++
configs/arm64/k3-am625-sk-linux-demo.c | 220 ++++++++++++
configs/arm64/k3-am625-sk.c | 317 ++++++++++++++++++
5 files changed, 800 insertions(+)
create mode 100644 configs/arm64/dts/inmate-k3-am625-sk-emmc.dts
create mode 100644 configs/arm64/dts/inmate-k3-am625-sk.dts
create mode 100644 configs/arm64/k3-am625-inmate-demo.c
create mode 100644 configs/arm64/k3-am625-sk-linux-demo.c
create mode 100644 configs/arm64/k3-am625-sk.c
diff --git a/configs/arm64/dts/inmate-k3-am625-sk-emmc.dts
b/configs/arm64/dts/inmate-k3-am625-sk-emmc.dts
new file mode 100644
index 00000000..2fb07d52
--- /dev/null
+++ b/configs/arm64/dts/inmate-k3-am625-sk-emmc.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+
+#include "inmate-k3-am625-sk.dts"
+
+/ {
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am62-sdhci";
+ reg = <0x0 0xfa10000 0x0 0x260>, <0x0 0xfa18000 0x0 0x134>;
+ power-domains = <&k3_pds 57 1>;
+ clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x9>;
+ ti,otap-del-sel-hs200 = <0x6>;
+ };
+};
+
+&sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ bus-width = <8>;
+ disable-wp;
+};
diff --git a/configs/arm64/dts/inmate-k3-am625-sk.dts
b/configs/arm64/dts/inmate-k3-am625-sk.dts
new file mode 100644
index 00000000..c1455073
--- /dev/null
+++ b/configs/arm64/dts/inmate-k3-am625-sk.dts
@@ -0,0 +1,163 @@
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ model = "Texas Instruments AM625 Inmate Model";
+ compatible = "ti,am625-evm", "ti,am625";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial1 = &main_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@e0000000 {
+ device_type = "memory";
+ reg = <0x0 0xe0000000 0x0 0x1fff0000>;
+ };
+
+ hypervisor {
+ compatible = "jailhouse,cell";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ device_type = "cpu";
+ enable-method = "psci";
+ };
+
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ /* Recommendation from GIC500 TRM Table A.3 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ cbass_main: interconnect@f0000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01880000 0x00 0xC0000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 152 1>;
+ current-speed = <115200>;
+ clock-frequency = <48000000>;
+ };
+
+ pci@76000000 {
+ compatible = "pci-host-ecam-generic";
+ device_type = "pci";
+ bus-range = <0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map =
+ <0 0 0 1 &gic500 GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 2 &gic500 GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 3 &gic500 GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <0 0 0 4 &gic500 GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x0 0x76000000 0x0 0x100000>;
+ ranges =
+ <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00
0x20000>;
+ };
+
+ dmss: bus@48000000 {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges = <0x00 0x48000000 0x00 0x48000000 0x00
0x06400000>;
+
+ ti,sci-dev-id = <25>;
+
+ secure_proxy_main: mailbox@4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_014";
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ dmsc: system-controller@44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <13>;
+ mbox-names = "rx", "tx";
+ mboxes = <&secure_proxy_main 14>,
+ <&secure_proxy_main 15>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+ };
+};
diff --git a/configs/arm64/k3-am625-inmate-demo.c
b/configs/arm64/k3-am625-inmate-demo.c
new file mode 100644
index 00000000..65cf4a7f
--- /dev/null
+++ b/configs/arm64/k3-am625-inmate-demo.c
@@ -0,0 +1,72 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for demo inmate on K3 based platforms.
+ * 1CPU, 64K RAM, 1 serial port(MCU UART 0).
+ *
+ * Copyright (c) 2019, 2022 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Authors:
+ * Nikhil Devshatwar <nikhil...@ti.com>
+ * Lokesh Vutla <lokeshvu...@ti.com>
+ * Matt Ranostay <mranos...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[3];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "inmate-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = 0,
+ .num_pci_devices = 0,
+
+ .console = {
+ .address = 0x02810000,
+ .divider = 0x1b,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0x4,
+ },
+
+ .mem_regions = {
+ /* MCU UART0 */ {
+ .phys_start = 0x02810000,
+ .virt_start = 0x02810000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {
+ .phys_start = 0xe0000000,
+ .virt_start = 0,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ }
+};
diff --git a/configs/arm64/k3-am625-sk-linux-demo.c
b/configs/arm64/k3-am625-sk-linux-demo.c
new file mode 100644
index 00000000..81f4e880
--- /dev/null
+++ b/configs/arm64/k3-am625-sk-linux-demo.c
@@ -0,0 +1,220 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Configuration for Linux inmate on AM625 based platforms
+ * 3 CPUs, 512MB RAM, 1 serial port (MAIN UART1)
+ *
+ * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Authors:
+ * Matt Ranostay <mranos...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+#ifndef CONFIG_INMATE_BASE
+#define CONFIG_INMATE_BASE 0x0000000
+#endif
+
+struct {
+ struct jailhouse_cell_desc cell;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[18];
+ struct jailhouse_irqchip irqchips[3];
+ struct jailhouse_pci_device pci_devices[2];
+} __attribute__((packed)) config = {
+ .cell = {
+ .signature = JAILHOUSE_CELL_DESC_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .name = "k3-am625-sk-linux-demo",
+ .flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .cpu_reset_address = 0x0,
+ .vpci_irq_base = 189 - 32,
+
+ .console = {
+ .address = 0x02810000,
+ .divider = 0x1b,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ },
+
+ .cpus = {
+ 0xe,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions for 00:00.0 (demo) */
+ {
+ .phys_start = 0xdfa00000,
+ .virt_start = 0xdfa00000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ {
+ .phys_start = 0xdfa10000,
+ .virt_start = 0xdfa10000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* Peer 0 */ {
+ .phys_start = 0xdfa20000,
+ .virt_start = 0xdfa20000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* Peer 1 */ {
+ .phys_start = 0xdfa30000,
+ .virt_start = 0xdfa30000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* Peer 2 */ {
+ .phys_start = 0xdfa40000,
+ .virt_start = 0xdfa40000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_ROOTSHARED,
+ },
+ /* IVSHMEM shared memory region for 00:01.0 */
+ JAILHOUSE_SHMEM_NET_REGIONS(0xdfb00000, 1),
+ /* RAM load */ {
+ .phys_start = 0xffff0000,
+ .virt_start = 0x0,
+ .size = 0x10000, /* 64KB */
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* RAM load */ {
+ .phys_start = 0xe0000000,
+ .virt_start = 0xe0000000,
+ .size = 0x1fff0000, /* (512MB - 64KB) */
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
+ JAILHOUSE_MEM_LOADABLE,
+ },
+ /* MCU UART0 */ {
+ .phys_start = 0x02810000,
+ .virt_start = 0x02810000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+#ifdef CONFIG_ENABLE_AM625_INMATE_CELL_EMMC
+ /* sdhci0 */ {
+ .phys_start = 0x0fa10000,
+ .virt_start = 0x0fa10000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* sdhci0 */ {
+ .phys_start = 0x0fa18000,
+ .virt_start = 0x0fa18000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+#endif
+ /* main sproxy target_data host_id=A53_3 */ {
+ .phys_start = 0x4d00e000,
+ .virt_start = 0x4d00e000,
+ .size = 0x3000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* main sproxy rt host_id=A53_3 */ {
+ .phys_start = 0x4a60e000,
+ .virt_start = 0x4a60e000,
+ .size = 0x3000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* main sproxy scfg host_id=A53_3 */ {
+ .phys_start = 0x4a40e000,
+ .virt_start = 0x4a40e000,
+ .size = 0x3000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* communication region */ {
+ .virt_start = 0x80000000,
+ .size = 0x1000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_COMM_REGION,
+ },
+ },
+
+ .irqchips = {
+ /*
+ * offset = (SPI_NR + 32 - base) / 32
+ * bit = (SPI_NR + 32 - base) % 32
+ */
+ {
+ .address = 0x01800000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0,
+ /* sproxy rx_014 */
+ 1 << (67 - 64),
+ 0, 0
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 160,
+ .pin_bitmap = {
+#ifdef CONFIG_ENABLE_AM625_INMATE_CELL_EMMC
+ /* sdhc */
+ 1 << (165 - 160) |
+#endif
+ /* vpci */
+ 1 << (189 - 160) |
+ 1 << (190 - 160),
+ /* uart */
+ 1 << (211 - 192),
+ 0, 0,
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 544,
+ .pin_bitmap = {
+ 0, 0, 0, 0,
+ },
+ },
+ },
+
+ .pci_devices = {
+ /* 00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX_64K,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 2,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ /* 00:01.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .bdf = 1 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX_64K,
+ .shmem_regions_start = 5,
+ .shmem_dev_id = 1,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
diff --git a/configs/arm64/k3-am625-sk.c b/configs/arm64/k3-am625-sk.c
new file mode 100644
index 00000000..2e5c3aef
--- /dev/null
+++ b/configs/arm64/k3-am625-sk.c
@@ -0,0 +1,317 @@
+/*
+ * Jailhouse, a Linux-based partitioning hypervisor
+ *
+ * Copyright (c) 2022 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Configuration for K3 based AM625 EVM
+ *
+ * Authors:
+ * Matt Ranostay <mranos...@ti.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include <jailhouse/types.h>
+#include <jailhouse/cell-config.h>
+
+struct {
+ struct jailhouse_system header;
+ __u64 cpus[1];
+ struct jailhouse_memory mem_regions[31];
+ struct jailhouse_irqchip irqchips[5];
+ struct jailhouse_pci_device pci_devices[2];
+} __attribute__((packed)) config = {
+ .header = {
+ .signature = JAILHOUSE_SYSTEM_SIGNATURE,
+ .revision = JAILHOUSE_CONFIG_REVISION,
+ .flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
+ .hypervisor_memory = {
+ .phys_start = 0xdfc00000,
+ .size = 0x400000,
+ },
+ .debug_console = {
+ .address = 0x02800000,
+ .size = 0x1000,
+ .type = JAILHOUSE_CON_TYPE_8250,
+ .flags = JAILHOUSE_CON_ACCESS_MMIO |
+ JAILHOUSE_CON_REGDIST_4,
+ },
+ .platform_info = {
+ .pci_mmconfig_base = 0x76000000,
+ .pci_mmconfig_end_bus = 0,
+ .pci_is_virtual = 1,
+ .pci_domain = 1,
+ .arm = {
+ .gic_version = 3,
+ .gicd_base = 0x01800000,
+ .gicr_base = 0x01880000,
+ .maintenance_irq = 25,
+ },
+ },
+ .root_cell = {
+ .name = "k3-am625-sk",
+
+ .cpu_set_size = sizeof(config.cpus),
+ .num_memory_regions = ARRAY_SIZE(config.mem_regions),
+ .num_irqchips = ARRAY_SIZE(config.irqchips),
+ .num_pci_devices = ARRAY_SIZE(config.pci_devices),
+ .vpci_irq_base = 180 - 32,
+ },
+ },
+
+ .cpus = {
+ 0xf,
+ },
+
+ .mem_regions = {
+ /* IVSHMEM shared memory regions for 00:00.0 (demo) */
+ {
+ .phys_start = 0xdfa00000,
+ .virt_start = 0xdfa00000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ {
+ .phys_start = 0xdfa10000,
+ .virt_start = 0xdfa10000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* Peer 0 */ {
+ .phys_start = 0xdfa20000,
+ .virt_start = 0xdfa20000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
+ },
+ /* Peer 1 */ {
+ .phys_start = 0xdfa30000,
+ .virt_start = 0xdfa30000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* Peer 2 */ {
+ .phys_start = 0xdfa40000,
+ .virt_start = 0xdfa40000,
+ .size = 0x10000,
+ .flags = JAILHOUSE_MEM_READ,
+ },
+ /* IVSHMEM shared memory region for 00:01.0 */
+ JAILHOUSE_SHMEM_NET_REGIONS(0xdfb00000, 0),
+ {
+ .phys_start = 0x01810000,
+ .virt_start = 0x01810000,
+ .size = 0x00070000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ {
+ .phys_start = 0x018a0000,
+ .virt_start = 0x018a0000,
+ .size = 0x00060000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* RAM */ {
+ .phys_start = 0x80000000,
+ .virt_start = 0x80000000,
+ .size = 0x5fa00000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* RAM. Reserved for inmates */ {
+ .phys_start = 0xe0000000,
+ .virt_start = 0xe0000000,
+ .size = 0x20000000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_EXECUTE,
+ },
+ /* ctrl mmr */ {
+ .phys_start = 0x000f0000,
+ .virt_start = 0x000f0000,
+ .size = 0x00030000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GPIO */ {
+ .phys_start = 0x00600000,
+ .virt_start = 0x00600000,
+ .size = 0x00002000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* GPU */ {
+ .phys_start = 0x0fd00000,
+ .virt_start = 0x0fd00000,
+ .size = 0x00020000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* TimeSync Router */ {
+ .phys_start = 0x00a40000,
+ .virt_start = 0x00a40000,
+ .size = 0x00001000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* First peripheral window, 1 of 2 */ {
+ .phys_start = 0x01000000,
+ .virt_start = 0x01000000,
+ .size = 0x00800000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* First peripheral window, 2 of 2 */ {
+ .phys_start = 0x01900000,
+ .virt_start = 0x01900000,
+ .size = 0x01229000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Second peripheral window */ {
+ .phys_start = 0x0e000000,
+ .virt_start = 0x0e000000,
+ .size = 0x01d00000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Third peripheral window */ {
+ .phys_start = 0x20000000,
+ .virt_start = 0x20000000,
+ .size = 0x0a008000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* OCSRAM */ {
+ .phys_start = 0x70000000,
+ .virt_start = 0x70000000,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* DSS */ {
+ .phys_start = 0x30200000,
+ .virt_start = 0x30200000,
+ .size = 0x00010000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* DMSS */ {
+ .phys_start = 0x48000000,
+ .virt_start = 0x48000000,
+ .size = 0x06400000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* PRUSS-M */ {
+ .phys_start = 0x30040000,
+ .virt_start = 0x30040000,
+ .size = 0x00080000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* USB */ {
+ .phys_start = 0x31000000,
+ .virt_start = 0x31000000,
+ .size = 0x00050000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* USB */ {
+ .phys_start = 0x31100000,
+ .virt_start = 0x31100000,
+ .size = 0x00050000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* CPSW */ {
+ .phys_start = 0x08000000,
+ .virt_start = 0x08000000,
+ .size = 0x00200000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* First Wake Up Domain */ {
+ .phys_start = 0x2b000000,
+ .virt_start = 0x2b000000,
+ .size = 0x00301000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* Second Wake Up Domain */ {
+ .phys_start = 0x43000000,
+ .virt_start = 0x43000000,
+ .size = 0x00020000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ /* MCU Domain Range */ {
+ .phys_start = 0x04000000,
+ .virt_start = 0x04000000,
+ .size = 0x01ff2000,
+ .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
+ JAILHOUSE_MEM_IO,
+ },
+ },
+
+ .irqchips = {
+ {
+ .address = 0x01800000,
+ .pin_base = 32,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 160,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 288,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 416,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ {
+ .address = 0x01800000,
+ .pin_base = 544,
+ .pin_bitmap = {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ },
+
+ .pci_devices = {
+ /* 0001:00:00.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 0 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX_64K,
+ .shmem_regions_start = 0,
+ .shmem_dev_id = 0,
+ .shmem_peers = 3,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
+ },
+ /* 0001:00:01.0 */ {
+ .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
+ .domain = 1,
+ .bdf = 1 << 3,
+ .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_INTX_64K,
+ .shmem_regions_start = 5,
+ .shmem_dev_id = 0,
+ .shmem_peers = 2,
+ .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
+ },
+ },
+};
--
2.30.2
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