From: Jan Kiszka <[email protected]> There is no 32-bit ARM board that we support and that has a GICv3. Very likely, such a board does not even exist and never will. So move the GICv3 support in Jailhouse to arm64, removing no longer needed abstractions.
Rather than stubbing a GICv3 for irqchip_cpu_init, use #ifdef in this case which is simpler and gives a more accurate error in case someone configures a v3 for ARM. Signed-off-by: Jan Kiszka <[email protected]> --- hypervisor/arch/arm-common/Kbuild | 4 +- hypervisor/arch/arm-common/include/asm/gic.h | 1 - hypervisor/arch/arm-common/irqchip.c | 2 + hypervisor/arch/arm/include/asm/arch_gicv3.h | 53 ------------------- hypervisor/arch/arm/traps.c | 13 ++--- hypervisor/arch/arm64/Kbuild | 2 +- .../arch/{arm-common => arm64}/gic-v3.c | 24 ++++----- .../arch/arm64/include/asm/arch_gicv3.h | 30 ----------- .../include/asm/gic_v3.h | 10 +++- hypervisor/arch/arm64/traps.c | 2 +- 10 files changed, 30 insertions(+), 111 deletions(-) delete mode 100644 hypervisor/arch/arm/include/asm/arch_gicv3.h rename hypervisor/arch/{arm-common => arm64}/gic-v3.c (97%) delete mode 100644 hypervisor/arch/arm64/include/asm/arch_gicv3.h rename hypervisor/arch/{arm-common => arm64}/include/asm/gic_v3.h (94%) diff --git a/hypervisor/arch/arm-common/Kbuild b/hypervisor/arch/arm-common/Kbuild index 9ddbc950..ee26b58c 100644 --- a/hypervisor/arch/arm-common/Kbuild +++ b/hypervisor/arch/arm-common/Kbuild @@ -1,7 +1,7 @@ # # Jailhouse, a Linux-based partitioning hypervisor # -# Copyright (c) Siemens AG, 2013-2017 +# Copyright (c) Siemens AG, 2013-2022 # # Authors: # Jan Kiszka <[email protected]> @@ -19,6 +19,6 @@ ccflags-$(CONFIG_JAILHOUSE_GCOV) += -fprofile-arcs -ftest-coverage objs-y += dbg-write.o lib.o psci.o control.o paging.o mmu_cell.o setup.o objs-y += irqchip.o pci.o ivshmem.o uart-pl011.o uart-xuartps.o uart-mvebu.o objs-y += uart-hscif.o uart-scifa.o uart-imx.o uart-imx-lpuart.o -objs-y += gic-v2.o gic-v3.o smccc.o +objs-y += gic-v2.o smccc.o common-objs-y = $(addprefix ../arm-common/,$(objs-y)) diff --git a/hypervisor/arch/arm-common/include/asm/gic.h b/hypervisor/arch/arm-common/include/asm/gic.h index e851d375..4eccde1b 100644 --- a/hypervisor/arch/arm-common/include/asm/gic.h +++ b/hypervisor/arch/arm-common/include/asm/gic.h @@ -50,6 +50,5 @@ extern void *gicd_base; extern spinlock_t dist_lock; void gic_handle_sgir_write(struct sgi *sgi); -bool gicv3_handle_sgir_write(u64 sgir); #endif /* !__ASSEMBLY__ */ #endif /* !_JAILHOUSE_ASM_GIC_COMMON_H */ diff --git a/hypervisor/arch/arm-common/irqchip.c b/hypervisor/arch/arm-common/irqchip.c index fdb15c9d..6e8c8534 100644 --- a/hypervisor/arch/arm-common/irqchip.c +++ b/hypervisor/arch/arm-common/irqchip.c @@ -330,9 +330,11 @@ int irqchip_cpu_init(struct per_cpu *cpu_data) case 2: irqchip = gicv2_irqchip; break; +#ifdef __aarch64__ case 3: irqchip = gicv3_irqchip; break; +#endif default: return trace_error(-EINVAL); } diff --git a/hypervisor/arch/arm/include/asm/arch_gicv3.h b/hypervisor/arch/arm/include/asm/arch_gicv3.h deleted file mode 100644 index 558bc047..00000000 --- a/hypervisor/arch/arm/include/asm/arch_gicv3.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Jailhouse, a Linux-based partitioning hypervisor - * - * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author: - * Lokesh Vutla <[email protected]> - * - * This work is licensed under the terms of the GNU GPL, version 2. See - * the COPYING file in the top-level directory. - */ - -#ifndef _JAILHOUSE_ASM_ARM_GIC_V3_H -#define _JAILHOUSE_ASM_ARM_GIC_V3_H - -#include <asm/sysregs.h> - -#define ICH_LR0_7(x) SYSREG_32(4, c12, c12, x) -#define ICH_LR8_15(x) SYSREG_32(4, c12, c13, x) -#define ICH_LRC0_7(x) SYSREG_32(4, c12, c14, x) -#define ICH_LRC8_15(x) SYSREG_32(4, c12, c15, x) - -#define ICC_SGI1R_EL1 SYSREG_64(0, c12) - -#define ARM_GIC_READ_LR0_7(n, val) do { \ - u32 lr##n, lrc##n; \ - \ - arm_read_sysreg(ICH_LR0_7(n), lr##n); \ - arm_read_sysreg(ICH_LRC0_7(n), lrc##n); \ - \ - val = ((u64)lrc##n << 32) | lr##n; \ -} while (0); - -#define ARM_GIC_WRITE_LR0_7(n, val) do { \ - arm_write_sysreg(ICH_LR0_7(n), (u32)val); \ - arm_write_sysreg(ICH_LRC0_7(n), val >> 32); \ -} while (0); - -#define ARM_GIC_READ_LR8_15(n, val) do { \ - u32 lr_##n, lrc_##n; \ - \ - arm_read_sysreg(ICH_LR8_15(n), lr_##n); \ - arm_read_sysreg(ICH_LRC8_15(n), lrc_##n); \ - \ - val = ((u64)lrc_##n << 32) | lr_##n; \ -} while (0); - -#define ARM_GIC_WRITE_LR8_15(n, val) do { \ - arm_write_sysreg(ICH_LR8_15(n), (u32)val); \ - arm_write_sysreg(ICH_LRC8_15(n), val >> 32); \ -} while (0); - -#endif /* _JAILHOUSE_ASM_ARM_GIC_V3_H */ diff --git a/hypervisor/arch/arm/traps.c b/hypervisor/arch/arm/traps.c index 6b402f74..c5f147b9 100644 --- a/hypervisor/arch/arm/traps.c +++ b/hypervisor/arch/arm/traps.c @@ -386,16 +386,9 @@ static enum trap_return arch_handle_cp15_64(struct trap_context *ctx) access_cell_reg(ctx, rt, &lo, true); access_cell_reg(ctx, rt2, &hi, true); - /* trapped by HCR.IMO/FMO */ - if (HSR_MATCH_MCRR_MRRC(ctx->hsr, 0, 12)) { /* ICC_SGI1R */ - if (!gicv3_handle_sgir_write(((u64)hi << 32) | lo)) - return TRAP_UNHANDLED; - } else { - /* trapped if HCR.TVM is set */ - if (!(CP15_64_PERFORM_WRITE(0, 2) || /* TTBR0 */ - CP15_64_PERFORM_WRITE(1, 2))) /* TTBR1 */ - return TRAP_UNHANDLED; - } + /* trapped if HCR.TVM is set: TTBR0 or TTBR1 */ + if (!(CP15_64_PERFORM_WRITE(0, 2) || CP15_64_PERFORM_WRITE(1, 2))) + return TRAP_UNHANDLED; arch_skip_instruction(ctx); diff --git a/hypervisor/arch/arm64/Kbuild b/hypervisor/arch/arm64/Kbuild index fd56a4da..6236dab6 100644 --- a/hypervisor/arch/arm64/Kbuild +++ b/hypervisor/arch/arm64/Kbuild @@ -20,5 +20,5 @@ always-y := lib.a # irqchip (common-objs-y), smmu-v3, ti-pvu, smmu, <generic units> lib-y := $(common-objs-y) -lib-y += entry.o setup.o control.o mmio.o paging.o caches.o traps.o +lib-y += entry.o setup.o control.o gic-v3.o mmio.o paging.o caches.o traps.o lib-y += iommu.o smmu-v3.o ti-pvu.o smmu.o diff --git a/hypervisor/arch/arm-common/gic-v3.c b/hypervisor/arch/arm64/gic-v3.c similarity index 97% rename from hypervisor/arch/arm-common/gic-v3.c rename to hypervisor/arch/arm64/gic-v3.c index 0429bb81..bdc25c8e 100644 --- a/hypervisor/arch/arm-common/gic-v3.c +++ b/hypervisor/arch/arm64/gic-v3.c @@ -45,9 +45,9 @@ static u64 gicv3_read_lr(unsigned int reg) u64 val; switch (reg) { -#define __READ_LR0_7(n) \ - case n: \ - ARM_GIC_READ_LR0_7(n, val) \ +#define __READ_LR0_7(n) \ + case n: \ + arm_read_sysreg(ICH_LR0_7_EL2(n), val); \ break; __READ_LR0_7(0) @@ -60,9 +60,9 @@ static u64 gicv3_read_lr(unsigned int reg) __READ_LR0_7(7) #undef __READ_LR0_7 -#define __READ_LR8_15(n) \ - case n+8: \ - ARM_GIC_READ_LR8_15(n, val) \ +#define __READ_LR8_15(n) \ + case n+8: \ + arm_read_sysreg(ICH_LR8_15_EL2(n), val); \ break; __READ_LR8_15(0) @@ -85,9 +85,9 @@ static u64 gicv3_read_lr(unsigned int reg) static void gicv3_write_lr(unsigned int reg, u64 val) { switch (reg) { -#define __WRITE_LR0_7(n) \ - case n: \ - ARM_GIC_WRITE_LR0_7(n, val) \ +#define __WRITE_LR0_7(n) \ + case n: \ + arm_write_sysreg(ICH_LR0_7_EL2(n), val); \ break; __WRITE_LR0_7(0) @@ -100,9 +100,9 @@ static void gicv3_write_lr(unsigned int reg, u64 val) __WRITE_LR0_7(7) #undef __WRITE_LR0_7 -#define __WRITE_LR8_15(n) \ - case n+8: \ - ARM_GIC_WRITE_LR8_15(n, val) \ +#define __WRITE_LR8_15(n) \ + case n+8: \ + arm_write_sysreg(ICH_LR8_15_EL2(n), val); \ break; __WRITE_LR8_15(0) __WRITE_LR8_15(1) diff --git a/hypervisor/arch/arm64/include/asm/arch_gicv3.h b/hypervisor/arch/arm64/include/asm/arch_gicv3.h deleted file mode 100644 index 93908232..00000000 --- a/hypervisor/arch/arm64/include/asm/arch_gicv3.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Jailhouse, a Linux-based partitioning hypervisor - * - * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author: - * Lokesh Vutla <[email protected]> - * - * This work is licensed under the terms of the GNU GPL, version 2. See - * the COPYING file in the top-level directory. - */ - -#ifndef _JAILHOUSE_ASM_ARM64_GIC_V3_H -#define _JAILHOUSE_ASM_ARM64_GIC_V3_H - -#include <asm/sysregs.h> - -#define ICH_LR0_7_EL2(x) SYSREG_64(4, c12, c12, x) -#define ICH_LR8_15_EL2(x) SYSREG_64(4, c12, c13, x) - -#define ICC_SGI1R_EL1 SYSREG_64(0, c12, c11, 5) - -#define ARM_GIC_READ_LR0_7(n, val) arm_read_sysreg(ICH_LR0_7_EL2(n), val); -#define ARM_GIC_WRITE_LR0_7(n, val) arm_write_sysreg(ICH_LR0_7_EL2(n), val); - -#define ARM_GIC_READ_LR8_15(n, val) arm_read_sysreg(ICH_LR8_15_EL2(n), val); -#define ARM_GIC_WRITE_LR8_15(n, val) \ - arm_write_sysreg(ICH_LR8_15_EL2(n), val); - -#endif /* _JAILHOUSE_ASM_ARM64_GIC_V3_H */ diff --git a/hypervisor/arch/arm-common/include/asm/gic_v3.h b/hypervisor/arch/arm64/include/asm/gic_v3.h similarity index 94% rename from hypervisor/arch/arm-common/include/asm/gic_v3.h rename to hypervisor/arch/arm64/include/asm/gic_v3.h index 853721d6..9672b219 100644 --- a/hypervisor/arch/arm-common/include/asm/gic_v3.h +++ b/hypervisor/arch/arm64/include/asm/gic_v3.h @@ -13,8 +13,8 @@ #ifndef _JAILHOUSE_ASM_GIC_V3_H #define _JAILHOUSE_ASM_GIC_V3_H +#include <jailhouse/types.h> #include <asm/sysregs.h> -#include <asm/arch_gicv3.h> #define GICDv3_CIDR0 0xfff0 #define GICDv3_PIDR0 0xffe0 @@ -69,6 +69,11 @@ #define ICH_AP1R2_EL2 SYSREG_32(4, c12, c9, 2) #define ICH_AP1R3_EL2 SYSREG_32(4, c12, c9, 3) +#define ICH_LR0_7_EL2(x) SYSREG_64(4, c12, c12, x) +#define ICH_LR8_15_EL2(x) SYSREG_64(4, c12, c13, x) + +#define ICC_SGI1R_EL1 SYSREG_64(0, c12, c11, 5) + #define ICC_CTLR_EOImode 0x2 #define ICC_PMR_MASK 0xff #define ICC_PMR_DEFAULT 0xf0 @@ -125,4 +130,7 @@ #define ICH_LR_PRIORITY_SHIFT 48 #define ICH_LR_SGI_EOI (0x1ULL << 41) #define ICH_LR_PHYS_ID_SHIFT 32 + +bool gicv3_handle_sgir_write(u64 sgir); + #endif /* _JAILHOUSE_ASM_GIC_V3_H */ diff --git a/hypervisor/arch/arm64/traps.c b/hypervisor/arch/arm64/traps.c index 488dd7f8..363a1b2a 100644 --- a/hypervisor/arch/arm64/traps.c +++ b/hypervisor/arch/arm64/traps.c @@ -15,7 +15,7 @@ #include <jailhouse/printk.h> #include <asm/control.h> #include <asm/entry.h> -#include <asm/gic.h> +#include <asm/gic_v3.h> #include <asm/mmio.h> #include <asm/psci.h> #include <asm/smccc.h> -- 2.36.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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