Hi We try to port TI RTOS application to hypervisor (inmate running on Core1). We have bizarre problems with interrupts. 1) If we use interrupt from timer, inmate got interrupts without any problem. Which is good. 2) if we use interrupt from Input pin (IRQ and I/O port are skipped as described in guidelines) we get interrupt *only if we have a context switch in rtos* (when RTOS re-enables interrupts when leaving some critical section). 3) sys_nirq1 is not delivered to inmate at all
>From Sitara perspective all interrupts: timer, GPIO Input and sys_nirq1 are delivered to GIC in the same way. Any idea? Some refence to explanation of mechanism (to doc or to code) of irq routing between cores would be highly appreciated? Best regards Rasty -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/f431434c-f52d-4d25-82c5-f8fae3bf1b16n%40googlegroups.com.
