Dear all,
During the last months we've been working at a refactoring and consolidation of
a series of patches for jailhouse aiming to improve predictability of the memory
subsystem under contention conditions for certain workloads.
The implemented extensions include cache-coloring (previously presented on the
mailing-list [0]) and performance-counter-based regulation ("Memguard" [1]). The
extensions cannot be considered production ready, but have served well in
several papers (e.g., [2,3,4,5]) and are reasonably stress-tested on ZCU102 and
S32V. Profiling of the workload and knowledge of the underlying hardware is
normally needed to achieve adequate isolation and predictability results as well
as good performance.
The latest rebase on "next" is available at
'https://gitlab.com/minervasys/public/jailhouse'
The extensions are a joint effort of Minerva Systems, Technical University of
Munich (TUM), Universita` di Modena e Reggio Emilia (Unimore), University of
Boston and are also based on previous work from UUIC and CVUT. AMD Xilinx
supported the first public version of cache-coloring developed at Unimore.
Minerva Systems will do a reasonable effort to keep them updated on top of
future versions of jailhouse, and if of interest, we’re open to discuss which
parts can be integrated upstream and provide some support for questions/issues
when using them.
Best regards,
Andrea
[0] https://groups.google.com/g/jailhouse-dev/c/MkvXIe7CR18/m/hMRUy1CzBAAJ
[1] H. Yun, G. Yao, R. Pellizzoni, M. Caccamo, and L. Sha, “MemGuard: Memory
bandwidth reservation system for efficient performance isolation in multi-core
platforms,” RTAS 2013
[2] T. Kloda, M. Solieri, R. Mancuso, N. Capodieci, P. Valente, and M. Bertogna,
"Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core
Embedded Systems," RTAS 2019
[3] P. Sohal, R. Tabish, U. Drepper, and R. Mancuso, "E-WarP: A System-wide
Framework for Memory Bandwidth Profiling and Management," RTSS 2020
[4] G. Schwaericke, R. Tabish, R. Pellizzoni, R. Mancuso, A. Bastoni, A. Zuepke,
and M. Caccamo, "A Real-Time virtio-based Framework for Predictable Inter-VM
Communication," RTSS 2021
[5] G. Ghaemi, D. Tarapore, and R. Mancuso, "Governing with Insights: Towards
Profile-Driven Cache Management of Black-Box Applications," ECRTS 2021
--
Dr. Andrea Bastoni
Research Fellow
Technische Universität München
Lehrstuhl für Cyber-Physical Systems in Production Engineering
Prof. Dr. Marco Caccamo
Boltzmannstr. 15,
Gebäude 1
85748 Garching
T: +49 89 289 55173
Email: [email protected]
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