Hi Nir,
On 29/11/2022 14:21, [email protected] wrote:
Hi there,
Our target is Sitara AM5726 , CortexA15 dual core on which we are
running Linux on A15 core0 and RTOS on core1.
__
RTOS gets periodic interrupt from external hardware via nirq1 pin
(dedicated input into ARM gic).____
Under heavy load in Linux (core 0!), RTOS, which runs on core1 misses
interrupts.____
Uhm. Can you reconstruct that issue w/o Jailhouse under Linux?
I mean, can you set the SMP affinity of that IRQ to core 1 under Linux,
and then write some test application running on core 1 that just
receives the IRQ. If that issue happens under Linux as well, then you
know that the issue has probably nothing to do with Jailhouse.
What also might happen: If there's enough pressure on the shared system
bus when Linux is under load, then you simply loose those IRQs as the
RTOS doesn't have enough time to handle it. You can test this hypothesis
if you lower the frequency of the the periodic interrupt. If you still
loose IRQs, then this should not be the case.
Questions____
1. Does linux/hypervisor participate in interrupt scheduling/forwarding
to cell on Core1____
Linux: No, Linux does not participate in anything that is going on on
CPU 1. That's the idea behind Jailhouse.
Jailhouse: Maybe. On ARM platforms, Jailhouse needs to reinject the
Interrupt from the hypervisor to the guest, if SDEI is not available.
Does the Sitara come with support for SDEI support?
(You can btw monitor the exits of the hypervisor with 'jailhouse cell
stats')
Ralf
2. Is there a description of interrupt forwarding/virtualization scheme
to cores (if exists)? Any pointer to document/source code would be
appreciated.
Thanks a lot,
Nir.
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