Hi, this is the first non-RFC series for RISC-V support in Jailhouse. The series was initially developed by Konrad Schwarz at SIEMENS in context of the SELENE project [0], and later extended by Stefan an me (see Contributors below) at OTH Regensburg.
The series relies on wip/new-cpu-config (by Jan, included), and can also be found here: https://github.com/lfd/jailhouse/tree/ralf/riscv/V15 We need some patches on top of Linux that can be found here: https://github.com/lfd/linux/tree/ralf/riscv-jailhouse/V21 This tree branches from Anup Patel's riscv_aia_v3 tree that adds the not yet integrated AIA support for Linux (support for APLIC and IMSIC), and comes with our standard Jailhouse patches on top. To test this series in Qemu, see instructions in [1]. Changes since RFC v2: - Full support for APLIC, including AIA/IMSIC - With APLIC AIA/IMSIC, we achieve zero traps under most conditions! (besides level-triggered wired IRQs) - Add support for Zicboz extension - Update configs; Upstream qemu changed some memory layouts - minor fixes and typos Changes since RFC v1: - Add support for SSTC (trapless timers) - Besides PLIC, add support for APLIC - minor fixes of typos - fix incorrect HSM state on cell reset - fix incorrect specifiers in spinlocks - fixes for some race conditions - Allow trap-free guest access to cycle counter - stats: Add more fine-granular accounting - vmm deactivation: fix bugs to get in running with -O2 - Add support for jailhouse-config-check The series adds support for: - RISC-V h-extensions (RV64 only) - MMU support: SV39, SV48, SV57 (provided by Qemu) - PLIC and APLIC interrupt controller - Multi-Core non-root cells - Basic demo inmates - Non-Root Linux support - IVSHMEM (IRQs are implemented by virtualising the PLIC, sigh…) Target platforms: - Qemu virtual targets What is missing and should be discussed: - Prioritisation of vIRQs: they always have lowest prio. vIRQ support is only suppported for testing / demonstration at the moment. Full virtualisation of the PLIC comes at a high cost, as priorities of the vIRQs need to be respectes as well. As this level of virtualisation is contrary to the concepts of Jailhouse, I deliberately did not implement prioritisation of vIRQs. Contributors: - Konrad Schwarz, Siemens (base support, first draft) - Ralf Ramsauer, OTH (exception handling, control flow, reworked PLIC support, APLIC support) - Stefan Huber, OTH (inmate support, APLIC support) - Jan Kiszka, Siemes (wip/new-cpu-config) Ralf [0] https://www.selene-project.eu/ [1] $ git clone https://github.com/lfd/jailv-testbed $ cd jailv-testbed $ git submodule init && git submodule update Have a riscv64-linux-gnu compiler ready, together with QEMU 7.2.0. If your distribution doesn't have this latest version, type $ ./do.sh qemu inside the testbed to get a working emulator. Compile the patches Linux kernel: $ ./do.sh prepare_linux $ ./do.sh linux Compile Jailhouse $ ./do.sh jailhouse Compile buildroot (required for root and non-root cell) $ ./do.sh prepare_buildroot $ ./do.sh buildroot And you're set. Test Jailhouse with: $ ./do.sh qemu_X_Y with X in {aplic, plic} and Y in {mc, uc} (e.g. ./do.sh aplic_qemu_mc). aplic will start the aplic variant, plic will start the plic variant. mc will start with six cores, uc will boot a single-core system (makes no sense in Jailhouse context, but great for debugging). Buildroot will start, inside the Buildroot root-cell, type: $ insmod jailhouse.ko $ jh-en # This script enables jailhouse, and automatically grabs the correct config $ jh-linux # This script starts a Linux non-root cell on HART 0 and 1 Jan Kiszka (20): core: Add internal event check before hypervisor activation core: Skip arch_flush_cell_vcpu_caches during setup x86: Do not kick targets of vcpu cache flushes core: Clarify invocation context of arch_flush_cell_vcpu_caches core: Convert config_commit into a unit callback arm64: Update unit link order comment and save a line arm, arm64: Make GICv3 arm64-only x86: Rename CPU_ID_INVALID to APIC_INVALID_CPU core: Beautify for_each_cpu helper core: Use statically sized cpu sets core: Move cell_init() of root cell from init_early to init_late core: Change CPU configuration to an array of structures driver: Convert to new CPU configuration format core: Convert to new CPU configuration format tools: Convert to new CPU configuration format configs: x86: Convert to new CPU configuration format configs: arm: Convert to new CPU configuration format configs: arm64: Convert to new CPU configuration format core: Optimize parsing of large CPU sets RISC-V cornerstone Konrad Schwarz (1): core: riscv: implement paging structures Ralf Ramsauer (50): driver: RISC-V: check for availability of h-extensions driver: sysfs: prepare for exit accounting on RISC-V driver: sysfs: fix cell statistic calculation core: riscv: define MMIO accessors core: riscv: Add CSR definitions core: riscv: introduce asm/bitops.h core: riscv: add processor.h core: riscv: Define percpu fields core: riscv: introduce global sbi_ecall.h core: riscv: introduce asm/sbi.h core: riscv: add platform information core: riscv: implement the hypercall interface core: riscv: introduce cell-specific fields core: riscv: add dbg-write helper core: riscv: implement library routines core: riscv: paging: add headers core: riscv: add asm-defines.c core: riscv: introduce traps.c core: riscv: Hypervisor entry code core: riscv: implement arch_send_event core: riscv: Add spinlock primitives Documentation: Add some documentation arm-common: export for_each_irqchip-macro core: riscv: introduce irqchip.h core: riscv: implement control.c core: forward original HV memory location core: riscv: implement setup.c core: riscv: Add irqchip abstraction layer core: riscv: Add PLIC implementation core: riscv: implement trap handlers inmates: riscv: add timer demo inmates: riscv: propagate hartid inmates: riscv: implement Linux Loader configs: riscv: qemu: add system configs configs: riscv: qemu: add inmate demo config configs: riscv: qemu: Add linux-demo core: riscv: add SSTC support core: riscv: PLIC: remove workaround driver: riscv: Add vPCI support core: riscv: implement APLIC support core: riscv: plic: introduce vIRQ support core: riscv: aplic: introduce vIRQ support configs: riscv: add ivshmem-net devices configs: riscv: add configs for APLIC+IMSIC core: riscv: Migrate IMSIC files, if IMSIC is available core: riscv: aplic: Add IMSIC support core: riscv: pci: Implement MSI-handling logic core: riscv: control: fix parking race condition core: riscv: setup: Add Qemu Workaround core: riscv: Add support for Zicboz extension Stefan Huber (2): inmates: riscv: implement tiny-demo RISC-V configs: riscv: Add configuration parameters for APLIC .gitignore | 1 + Documentation/hypervisor-interfaces.txt | 16 +- Documentation/memory-layout.txt | 20 +- configs/arm/bananapi-inmate-demo.c | 10 +- configs/arm/bananapi-linux-demo.c | 10 +- configs/arm/bananapi.c | 13 +- configs/arm/emtrion-rzg1e-inmate-demo.c | 8 +- configs/arm/emtrion-rzg1e-linux-demo.c | 8 +- configs/arm/emtrion-rzg1e.c | 11 +- configs/arm/emtrion-rzg1h-inmate-demo.c | 8 +- configs/arm/emtrion-rzg1h-linux-demo.c | 8 +- configs/arm/emtrion-rzg1h.c | 29 +- configs/arm/emtrion-rzg1m-inmate-demo.c | 8 +- configs/arm/emtrion-rzg1m-linux-demo.c | 8 +- configs/arm/emtrion-rzg1m.c | 11 +- configs/arm/jetson-tk1-inmate-demo.c | 10 +- configs/arm/jetson-tk1-linux-demo.c | 13 +- configs/arm/jetson-tk1.c | 19 +- configs/arm/orangepi0-inmate-demo.c | 10 +- configs/arm/orangepi0-linux-demo.c | 13 +- configs/arm/orangepi0.c | 19 +- configs/arm/qemu-arm-inmate-demo.c | 10 +- configs/arm/qemu-arm-linux-demo.c | 13 +- configs/arm/qemu-arm.c | 31 +- configs/arm64/amd-seattle-inmate-demo.c | 8 +- configs/arm64/amd-seattle-linux-demo.c | 11 +- configs/arm64/amd-seattle.c | 29 +- configs/arm64/espressobin-inmate-demo.c | 10 +- configs/arm64/espressobin-linux-demo.c | 10 +- configs/arm64/espressobin.c | 13 +- configs/arm64/foundation-v8-inmate-demo.c | 8 +- configs/arm64/foundation-v8-linux-demo.c | 11 +- configs/arm64/foundation-v8.c | 17 +- configs/arm64/hikey-inmate-demo.c | 10 +- configs/arm64/hikey-linux-demo.c | 13 +- configs/arm64/hikey.c | 31 +- configs/arm64/imx8dxl-inmate-demo.c | 8 +- configs/arm64/imx8dxl.c | 13 +- configs/arm64/imx8mm-inmate-demo.c | 8 +- configs/arm64/imx8mm-linux-demo.c | 11 +- configs/arm64/imx8mm.c | 19 +- configs/arm64/imx8mn-inmate-demo.c | 8 +- configs/arm64/imx8mn-linux-demo.c | 11 +- configs/arm64/imx8mn.c | 19 +- configs/arm64/imx8mp-inmate-demo.c | 8 +- configs/arm64/imx8mp-linux-demo.c | 11 +- configs/arm64/imx8mp.c | 19 +- configs/arm64/imx8mq-inmate-demo.c | 8 +- configs/arm64/imx8mq-linux-demo.c | 11 +- configs/arm64/imx8mq.c | 19 +- configs/arm64/imx8qm-inmate-demo.c | 8 +- configs/arm64/imx8qm-linux-demo.c | 11 +- configs/arm64/imx8qm.c | 25 +- configs/arm64/jetson-tx1-inmate-demo.c | 8 +- configs/arm64/jetson-tx1-linux-demo.c | 11 +- configs/arm64/jetson-tx1.c | 17 +- configs/arm64/jetson-tx2-inmate-demo.c | 8 +- configs/arm64/jetson-tx2.c | 17 +- configs/arm64/k3-am625-sk-inmate-demo.c | 8 +- configs/arm64/k3-am625-sk-linux-demo.c | 11 +- configs/arm64/k3-am625-sk.c | 17 +- configs/arm64/k3-am654-idk-inmate-demo.c | 8 +- configs/arm64/k3-am654-idk-linux-demo.c | 11 +- configs/arm64/k3-am654-idk.c | 17 +- configs/arm64/k3-j7200-evm-inmate-demo.c | 8 +- configs/arm64/k3-j7200-evm-linux-demo.c | 8 +- configs/arm64/k3-j7200-evm.c | 11 +- configs/arm64/k3-j721e-evm-inmate-demo.c | 8 +- configs/arm64/k3-j721e-evm-linux-demo.c | 8 +- configs/arm64/k3-j721e-evm.c | 11 +- configs/arm64/ls1028a-rdb-inmate-demo.c | 8 +- configs/arm64/ls1028a-rdb-linux-demo.c | 8 +- configs/arm64/ls1028a-rdb.c | 13 +- configs/arm64/ls1043a-rdb-dpaa-linux-demo.c | 11 +- configs/arm64/ls1043a-rdb-inmate-demo.c | 8 +- configs/arm64/ls1043a-rdb-linux-demo.c | 11 +- configs/arm64/ls1043a-rdb.c | 19 +- configs/arm64/ls1046a-rdb-inmate-demo.c | 8 +- configs/arm64/ls1046a-rdb-linux-demo.c | 11 +- configs/arm64/ls1046a-rdb.c | 19 +- configs/arm64/ls1088a-rdb-inmate-demo.c | 8 +- configs/arm64/ls1088a-rdb-linux-demo.c | 11 +- configs/arm64/ls1088a-rdb.c | 29 +- configs/arm64/ls2088a-rdb-inmate-demo.c | 8 +- configs/arm64/ls2088a-rdb-linux-demo.c | 11 +- configs/arm64/ls2088a-rdb.c | 29 +- configs/arm64/macchiatobin-inmate-demo.c | 10 +- configs/arm64/macchiatobin-linux-demo.c | 13 +- configs/arm64/macchiatobin.c | 19 +- .../arm64/miriac-sbc-ls1046a-inmate-demo.c | 8 +- configs/arm64/miriac-sbc-ls1046a-linux-demo.c | 11 +- configs/arm64/miriac-sbc-ls1046a.c | 17 +- configs/arm64/pine64-plus-inmate-demo.c | 8 +- configs/arm64/pine64-plus-linux-demo.c | 11 +- configs/arm64/pine64-plus.c | 17 +- configs/arm64/qemu-arm64-inmate-demo.c | 10 +- configs/arm64/qemu-arm64-linux-demo.c | 13 +- configs/arm64/qemu-arm64-zephyr-demo.c | 11 +- configs/arm64/qemu-arm64.c | 55 +- configs/arm64/renesas-r8a774a1-inmate-demo.c | 8 +- configs/arm64/renesas-r8a774a1-linux-demo.c | 17 +- configs/arm64/renesas-r8a774a1.c | 23 +- configs/arm64/rpi4-inmate-demo.c | 10 +- configs/arm64/rpi4-linux-demo.c | 13 +- configs/arm64/rpi4.c | 19 +- configs/arm64/ultra96-inmate-demo.c | 10 +- configs/arm64/ultra96-linux-demo.c | 13 +- configs/arm64/ultra96.c | 19 +- configs/arm64/zynqmp-zcu102-inmate-demo.c | 10 +- configs/arm64/zynqmp-zcu102-linux-demo-2.c | 10 +- configs/arm64/zynqmp-zcu102-linux-demo.c | 13 +- configs/arm64/zynqmp-zcu102.c | 19 +- .../dts/qemu-linux-inmate-aplic-imsic.dts | 124 +++ configs/riscv/dts/qemu-linux-inmate-aplic.dts | 111 +++ configs/riscv/dts/qemu-linux-inmate-plic.dts | 112 +++ configs/riscv/qemu-aplic-imsic-mc.c | 5 + configs/riscv/qemu-aplic-imsic-uc.c | 5 + configs/riscv/qemu-aplic-mc.c | 4 + configs/riscv/qemu-aplic-uc.c | 4 + configs/riscv/qemu-imsic.h | 46 + configs/riscv/qemu-inmate-demo-aplic-imsic.c | 3 + configs/riscv/qemu-inmate-demo.c | 1 + configs/riscv/qemu-inmate-demo.h | 66 ++ configs/riscv/qemu-layout.h | 33 + configs/riscv/qemu-linux-demo-aplic-imsic.c | 4 + configs/riscv/qemu-linux-demo-aplic.c | 3 + configs/riscv/qemu-linux-demo-plic.c | 3 + configs/riscv/qemu-linux-demo.h | 146 ++++ configs/riscv/qemu-plic-mc.c | 4 + configs/riscv/qemu-plic-uc.c | 4 + configs/riscv/qemu.h | 322 +++++++ configs/x86/apic-demo.c | 10 +- configs/x86/e1000-demo.c | 10 +- configs/x86/f2a88xm-hd3.c | 19 +- configs/x86/imb-a180.c | 19 +- configs/x86/ioapic-demo.c | 10 +- configs/x86/ivshmem-demo.c | 10 +- configs/x86/linux-x86-demo.c | 13 +- configs/x86/pci-demo.c | 10 +- configs/x86/qemu-x86.c | 19 +- configs/x86/smp-demo.c | 16 +- configs/x86/tiny-demo.c | 10 +- driver/cell.c | 20 +- driver/main.c | 106 ++- driver/main.h | 9 +- driver/pci.c | 33 +- driver/sysfs.c | 51 +- hypervisor/arch/arm-common/Kbuild | 4 +- hypervisor/arch/arm-common/control.c | 22 +- hypervisor/arch/arm-common/gic-v2.c | 2 +- hypervisor/arch/arm-common/include/asm/gic.h | 1 - .../arch/arm-common/include/asm/iommu.h | 1 - .../arch/arm-common/include/asm/irqchip.h | 2 - hypervisor/arch/arm-common/irqchip.c | 13 +- hypervisor/arch/arm-common/lib.c | 6 +- hypervisor/arch/arm-common/psci.c | 13 +- hypervisor/arch/arm/include/asm/arch_gicv3.h | 53 -- hypervisor/arch/arm/include/asm/types.h | 4 +- hypervisor/arch/arm/iommu.c | 4 - hypervisor/arch/arm/traps.c | 13 +- hypervisor/arch/arm64/Kbuild | 9 +- .../arch/{arm-common => arm64}/gic-v3.c | 48 +- .../arch/arm64/include/asm/arch_gicv3.h | 30 - .../include/asm/gic_v3.h | 10 +- hypervisor/arch/arm64/include/asm/ti-pvu.h | 2 - hypervisor/arch/arm64/include/asm/types.h | 2 + hypervisor/arch/arm64/iommu.c | 7 - hypervisor/arch/arm64/paging.c | 5 +- hypervisor/arch/arm64/smmu-v3.c | 1 + hypervisor/arch/arm64/smmu.c | 7 +- hypervisor/arch/arm64/ti-pvu.c | 14 +- hypervisor/arch/arm64/traps.c | 2 +- hypervisor/arch/riscv/Kbuild | 18 + hypervisor/arch/riscv/Makefile | 13 + hypervisor/arch/riscv/aplic.c | 790 +++++++++++++++++ hypervisor/arch/riscv/asm-defines.c | 46 + hypervisor/arch/riscv/control.c | 277 ++++++ hypervisor/arch/riscv/dbg-write.c | 33 + hypervisor/arch/riscv/entry.S | 421 +++++++++ hypervisor/arch/riscv/exception.S | 91 ++ hypervisor/arch/riscv/include/asm/bitops.h | 75 ++ hypervisor/arch/riscv/include/asm/cell.h | 45 + .../smmu.h => riscv/include/asm/control.h} | 9 +- hypervisor/arch/riscv/include/asm/csr64.h | 222 +++++ hypervisor/arch/riscv/include/asm/irqchip.h | 119 +++ hypervisor/arch/riscv/include/asm/ivshmem.h | 15 + .../arch/riscv/include/asm/jailhouse_header.h | 32 + hypervisor/arch/riscv/include/asm/mmio.h | 67 ++ hypervisor/arch/riscv/include/asm/paging.h | 138 +++ .../arch/riscv/include/asm/paging_modes.h | 18 + hypervisor/arch/riscv/include/asm/percpu.h | 64 ++ hypervisor/arch/riscv/include/asm/processor.h | 105 +++ hypervisor/arch/riscv/include/asm/sbi.h | 86 ++ hypervisor/arch/riscv/include/asm/sections.h | 14 + hypervisor/arch/riscv/include/asm/setup.h | 16 + hypervisor/arch/riscv/include/asm/spinlock.h | 75 ++ hypervisor/arch/riscv/include/asm/types.h | 15 + hypervisor/arch/riscv/irqchip.c | 247 ++++++ hypervisor/arch/riscv/ivshmem.c | 63 ++ hypervisor/arch/riscv/lib.c | 36 + hypervisor/arch/riscv/paging.c | 278 ++++++ hypervisor/arch/riscv/pci.c | 123 +++ hypervisor/arch/riscv/plic.c | 495 +++++++++++ hypervisor/arch/riscv/setup.c | 273 ++++++ hypervisor/arch/riscv/traps.c | 827 ++++++++++++++++++ hypervisor/arch/x86/amd_iommu.c | 4 +- hypervisor/arch/x86/apic.c | 24 +- hypervisor/arch/x86/cat.c | 5 +- hypervisor/arch/x86/control.c | 26 +- hypervisor/arch/x86/include/asm/apic.h | 4 +- hypervisor/arch/x86/include/asm/control.h | 4 +- hypervisor/arch/x86/include/asm/ioapic.h | 4 +- hypervisor/arch/x86/include/asm/iommu.h | 2 - hypervisor/arch/x86/include/asm/types.h | 4 +- hypervisor/arch/x86/ioapic.c | 4 +- hypervisor/arch/x86/iommu.c | 4 +- hypervisor/arch/x86/svm.c | 6 +- hypervisor/arch/x86/test-device.c | 3 +- hypervisor/arch/x86/vmx.c | 4 +- hypervisor/arch/x86/vtd.c | 4 +- hypervisor/control.c | 108 +-- hypervisor/include/jailhouse/cell.h | 8 +- hypervisor/include/jailhouse/control.h | 36 +- hypervisor/include/jailhouse/gen-defines.h | 8 +- hypervisor/include/jailhouse/header.h | 7 + hypervisor/include/jailhouse/mmio.h | 4 + hypervisor/include/jailhouse/paging.h | 2 +- hypervisor/include/jailhouse/pci.h | 4 +- hypervisor/include/jailhouse/percpu.h | 4 +- hypervisor/include/jailhouse/processor.h | 4 +- hypervisor/include/jailhouse/types.h | 14 +- hypervisor/include/jailhouse/unit.h | 7 +- hypervisor/pci.c | 11 +- hypervisor/setup.c | 22 +- include/arch/riscv/asm/jailhouse_hypercall.h | 113 +++ include/arch/riscv/asm/sbi_ecall.h | 96 ++ include/jailhouse/cell-config.h | 42 +- include/jailhouse/console.h | 1 + inmates/demos/riscv/Makefile | 20 + inmates/demos/riscv/timer-demo.c | 57 ++ inmates/demos/riscv/tiny-demo.c | 19 + inmates/lib/include/inmate_common.h | 1 + inmates/lib/riscv/Makefile | 46 + inmates/lib/riscv/Makefile.lib | 64 ++ inmates/lib/riscv/header.S | 76 ++ inmates/lib/riscv/include/inmate.h | 184 ++++ inmates/lib/riscv/inmate.lds.S | 77 ++ inmates/lib/riscv/irq.c | 107 +++ inmates/lib/riscv/printk.c | 61 ++ inmates/lib/riscv/setup.c | 45 + inmates/lib/riscv/uart.c | 47 + inmates/tests/riscv/Makefile | 0 inmates/tools/riscv/Makefile | 19 + inmates/tools/riscv/linux-loader.c | 25 + pyjailhouse/config_parser.py | 45 +- pyjailhouse/sysfs_parser.py | 20 +- scripts/include.mk | 3 + tools/jailhouse-config-check | 6 + tools/jailhouse-config-create | 14 +- tools/root-cell-config.c.tmpl | 15 +- 260 files changed, 8913 insertions(+), 898 deletions(-) create mode 100644 configs/riscv/dts/qemu-linux-inmate-aplic-imsic.dts create mode 100644 configs/riscv/dts/qemu-linux-inmate-aplic.dts create mode 100644 configs/riscv/dts/qemu-linux-inmate-plic.dts create mode 100644 configs/riscv/qemu-aplic-imsic-mc.c create mode 100644 configs/riscv/qemu-aplic-imsic-uc.c create mode 100644 configs/riscv/qemu-aplic-mc.c create mode 100644 configs/riscv/qemu-aplic-uc.c create mode 100644 configs/riscv/qemu-imsic.h create mode 100644 configs/riscv/qemu-inmate-demo-aplic-imsic.c create mode 100644 configs/riscv/qemu-inmate-demo.c create mode 100644 configs/riscv/qemu-inmate-demo.h create mode 100644 configs/riscv/qemu-layout.h create mode 100644 configs/riscv/qemu-linux-demo-aplic-imsic.c create mode 100644 configs/riscv/qemu-linux-demo-aplic.c create mode 100644 configs/riscv/qemu-linux-demo-plic.c create mode 100644 configs/riscv/qemu-linux-demo.h create mode 100644 configs/riscv/qemu-plic-mc.c create mode 100644 configs/riscv/qemu-plic-uc.c create mode 100644 configs/riscv/qemu.h delete mode 100644 hypervisor/arch/arm/include/asm/arch_gicv3.h rename hypervisor/arch/{arm-common => arm64}/gic-v3.c (95%) delete mode 100644 hypervisor/arch/arm64/include/asm/arch_gicv3.h rename hypervisor/arch/{arm-common => arm64}/include/asm/gic_v3.h (94%) create mode 100644 hypervisor/arch/riscv/Kbuild create mode 100644 hypervisor/arch/riscv/Makefile create mode 100644 hypervisor/arch/riscv/aplic.c create mode 100644 hypervisor/arch/riscv/asm-defines.c create mode 100644 hypervisor/arch/riscv/control.c create mode 100644 hypervisor/arch/riscv/dbg-write.c create mode 100644 hypervisor/arch/riscv/entry.S create mode 100644 hypervisor/arch/riscv/exception.S create mode 100644 hypervisor/arch/riscv/include/asm/bitops.h create mode 100644 hypervisor/arch/riscv/include/asm/cell.h rename hypervisor/arch/{arm64/include/asm/smmu.h => riscv/include/asm/control.h} (58%) create mode 100644 hypervisor/arch/riscv/include/asm/csr64.h create mode 100644 hypervisor/arch/riscv/include/asm/irqchip.h create mode 100644 hypervisor/arch/riscv/include/asm/ivshmem.h create mode 100644 hypervisor/arch/riscv/include/asm/jailhouse_header.h create mode 100644 hypervisor/arch/riscv/include/asm/mmio.h create mode 100644 hypervisor/arch/riscv/include/asm/paging.h create mode 100644 hypervisor/arch/riscv/include/asm/paging_modes.h create mode 100644 hypervisor/arch/riscv/include/asm/percpu.h create mode 100644 hypervisor/arch/riscv/include/asm/processor.h create mode 100644 hypervisor/arch/riscv/include/asm/sbi.h create mode 100644 hypervisor/arch/riscv/include/asm/sections.h create mode 100644 hypervisor/arch/riscv/include/asm/setup.h create mode 100644 hypervisor/arch/riscv/include/asm/spinlock.h create mode 100644 hypervisor/arch/riscv/include/asm/types.h create mode 100644 hypervisor/arch/riscv/irqchip.c create mode 100644 hypervisor/arch/riscv/ivshmem.c create mode 100644 hypervisor/arch/riscv/lib.c create mode 100644 hypervisor/arch/riscv/paging.c create mode 100644 hypervisor/arch/riscv/pci.c create mode 100644 hypervisor/arch/riscv/plic.c create mode 100644 hypervisor/arch/riscv/setup.c create mode 100644 hypervisor/arch/riscv/traps.c create mode 100644 include/arch/riscv/asm/jailhouse_hypercall.h create mode 100644 include/arch/riscv/asm/sbi_ecall.h create mode 100644 inmates/demos/riscv/Makefile create mode 100644 inmates/demos/riscv/timer-demo.c create mode 100644 inmates/demos/riscv/tiny-demo.c create mode 100644 inmates/lib/riscv/Makefile create mode 100644 inmates/lib/riscv/Makefile.lib create mode 100644 inmates/lib/riscv/header.S create mode 100644 inmates/lib/riscv/include/inmate.h create mode 100644 inmates/lib/riscv/inmate.lds.S create mode 100644 inmates/lib/riscv/irq.c create mode 100644 inmates/lib/riscv/printk.c create mode 100644 inmates/lib/riscv/setup.c create mode 100644 inmates/lib/riscv/uart.c create mode 100644 inmates/tests/riscv/Makefile create mode 100644 inmates/tools/riscv/Makefile create mode 100644 inmates/tools/riscv/linux-loader.c -- 2.40.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. 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