> The problem is the cache flush/ invalidation which is performed locally > and signal to the other CPUs in the same cacheable domain. This is > required on SMP systems where the memory is shared between CPUs but can > be omitted in setup where each CPU has exclusive memory.
You might want to take a look at the patches in this thread: https://lore.kernel.org/linux-arm-kernel/[email protected]/t/#u They address the same problem but offer a kernel-only solution (rough summary: tlbi broadcast instructions are only issued if more than one CPU is online in Linux). The obvious advantage is that it doesn’t rely on the cooperation of Linux and the hypervisor. There may even be a chance that they make it into mainline. Oliver -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/BD7FE16F-42F5-4D5C-9182-2AFC442B43BC%40gmx.de.
