Hi Alex, > Subject: Re: str wzr, [x1, #16]! triggers EL2 unhandled data abort > > Hi Peng, > > Am 12.12.23 um 03:42 schrieb Peng Fan: > > Hi All, > > > > > > I am running jailhouse on i.MX9 Cortex-A55, and meet an issue. > > " str wzr, [x1, #16]! " this instruction in EL0 triggers unhanlded > > Data abort in EL2, with ISS is data abort, ISV is 0. > > > > I am not sure why this instruction trigger DC with ISV 0. > > Any ideas are appreciated. > > > > Thanks, > > Peng. > > The Arm architecture cannot provide all information in ISS for instructions > that also update the base register.
Does ARM architecture TRM note this? Would you please share me the Chapter? > > You need to change the code sequence to: > str wzr, [x1, #16] > add x1, x1, #16 Hmm, but gcc generates "str wzr, [x1, #16]!" from c code. This should be common issue I think. Thanks, Peng. > > > Best regards > Alex -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/DU0PR04MB9417F5A4D0C801E59F32E6F2888EA%40DU0PR04MB9417.eurprd04.prod.outlook.com.
