Hi,
I checked again the configs with jailhouse config check and nothing came
up. I'm attaching the configurations.
Thanks,
Michele
Il giorno mercoledì 17 gennaio 2024 alle 11:52:18 UTC+1 Ralf Ramsauer ha
scritto:
> Hi Michele,
>
> On 16/01/2024 20:44, Michele Pescapè wrote:
> > Hi,
> >
> > I'm trying to give network access to the non root cell, however it seems
> > that I'm not able to pass the right PCI device. It always defaults to
> > taking away the 00:00.0 pci device from the root cell causing a crash
> > for the root cell.
> >
> > In both the root and non root cell's configs I added the shared memory
> > regions using the macro JAILHOUSE_SHMEM_NET_REGIONS(0x60000000, 0) for
> > the root and using dev_id=1 for the non root. The resulting regions do
> > not overlap other memory regions, config check does not return any
> errors.
> >
> > I also added the following PCI device in both cells, where
> > .shmem_regions_start is assigned to the correct index for the first
> > shared memory region created using the aforementioned macro.
> >
> > /* IVSHMEM: 00:05.0 */
> > {
> > .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
> > .domain = 0x0,
> > .bdf = 0x28,
>
> […]
>
> > .bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
> > .num_msix_vectors = 2,
> > .shmem_regions_start = 0,
> > .shmem_dev_id = 0, (1 in the non root cell)
> > .shmem_peers = 2,
> > .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
> > },
> >
> > I tried using different values for the .bdf, none of which were already
> > used by other devices but none worked. The root cell always sees the new
> > device correctly when starting the hypervisor, I can also see it with
> > lspci and ifconfig, however once I issue the cell linux command to start
> > the non root cell, I get the following output followed by a streak of
> > errors from the hypervisor, forcing a manual reset.
> >
> > Removing PCI device 00:00.0 from cell "RootCell"
> > Adding PCI device 00:00.0 to cell "linux-1"
>
> .bdf = 0x28 doesn't correspond with 00:00.0. Would you please test your
> current configs against jailhouse-config-check, and in case of no
> errors, would you please attach the current versions again?
>
> Thanks,
> Ralf
>
> > FATAL: unable to get MMIO instruction
> > FATAL: Invalid MMIO/RAM write, addr: 0x0000000106d8c020 size: 0
> > RIP: 0xffffffffa910ff4c RSP: 0xffffab85400f7de0 FLAGS: 93
> > RAX: 0x0000000000000000 RBX: 0x000000000002f170 RCX: 0x0000000000000040
> > RDX: 0x0000000000000414 RSI: 0xffff8b6000955400 RDI: 0x0000000000000001
> > CS: 10 BASE: 0x0000000000000000 AR-BYTES: 29b EFER.LMA 1
> > CR0: 0x0000000080050033 CR3: 0x0000000106d8c000 CR4: 0x00000000003506a0
> > EFER: 0x0000000000001d01
> > Parking CPU 4 (Cell: "RootCell")
> > (etc..)
> >
> > I'm not sure what I'm missing here, CONFIG_IVSHMEM_NET is enabled in
> > both the root and non root kernel config, I also enabled
> > CONFIG_PCI_HOST_GENERIC in the root linux as suggested in one of the
> > conversations on this site.
> >
> > Thanks,
> > Michele
> >
> >
> > Il giorno domenica 14 gennaio 2024 alle 15:49:40 UTC+1 Ralf Ramsauer ha
> > scritto:
> >
> > Hi Michele,
> >
> > On 14/01/2024 02:18, Michele Pescapè wrote:
> > > Hi,
> > >
> > > There were PIO writes to ports 4e,4f,2e and 2f, each of size 1
> > and each
> > > one on subsequent restarts. I'm not sure how to figure out what they
> > > belong to.
> >
> > Easy and straight forward: Read the jailhouse crash dump.
> >
> > Look at the program counter, and maybe the return address. Disassemble
> > your kernel (objdump -d vmlinux) and lookup that address. Now you know
> > the name of the routine in the kernel that caused the crash.
> >
> > Don't simply whitelist ports. Only whitelist them, if you're sure what
> > you're doing.
> >
> > >
> > > CONFIG_ISA_DMA_API is already disabled.
> > >
> > > I missed the irqchip for the uart. However as of right now I just
> > copied
> > > the whole fragment from the root configuration which means I
> > could be
> > > taking away other interrupts from the root cell, I still have to
> > figure
> > > out how to tune that
> > >
> > > /* IOAPIC 13, GSI base 0 */
> > > {
> > > .address = 0xfec00000,
> > > .id = 0xa0,
> > > .pin_bitmap = {
> > > 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
> >
> > With this, you take away ALL interrupts from the root cell, which you
> > don't want to do, you only want to take away the interrupt that
> > corresponds to ttyS0 (i.e. Port 0x3f8).
> >
> > See here: https://en.wikipedia.org/wiki/COM_(hardware_interface)
> > <https://en.wikipedia.org/wiki/COM_(hardware_interface)>
> >
> > COM1: I/O port 0x3F8, IRQ 4
> >
> > So you want to only assign IRQ 4 to your non-root cell. See
> > linux-x86-demo.c to see how that works.
> >
> > > },
> > > },
> > >
> > > Still, now I can finally login into the non root linux.
> >
> > Excellent!
> >
> > Ralf
> >
> > >
> > > Thanks,
> > > Michele
> > >
> > > Il giorno sabato 13 gennaio 2024 alle 21:09:28 UTC+1 Ralf
> > Ramsauer ha
> > > scritto:
> > >
> > > Hi Michele,
> > >
> > > On 13/01/2024 18:08, Michele Pescapè wrote:
> > > > Hi,
> > > >
> > > > The problem was that the ram regions in the non root configuration
> > > > weren't detected as such because of the missing JAILHOUSE_MEM_DMA
> > > flag.
> > >
> > > Yikes, makes sense.
> > >
> > > > After adding that, I also had to add two pio_regions because
> > the non
> > > > root linux was crashing because of two ports which aren't
> > present in
> > > > /proc/ioports.
> > >
> > > Uhm - which PIO ports? Don't simply assign PIO ports. There must
> > be a
> > > reason for them. What ports did crash?
> > >
> > > Did you disable(!) CONFIG_ISA_DMA_API? Please disable it. Therefore,
> > > you
> > > have to activate CONFIG_EXPERT first.
> > >
> > > I *bet* it was i8237…
> > >
> > > > I also had to add mce=off to the command line because i had an
> > > unhandled
> > >
> > > or disable CONFIG_X86_MCE.
> > >
> > > > MSR error, I'll have to disable that in the kernel config.
> > > > At this point the non root linux seems to start, I see the boot
> > > log. No
> > >
> > > Excellent!
> > >
> > > > way of interacting with it as there is not a login prompt or
> > > anything, I
> > > > think I need to ssh to the cell at this point, right?
> > >
> > > Was the initramdisk loaded correctly?
> > >
> > > Did you assign - in your non-root cell config - the irqchip and the
> > > corresponding interrupts of the uart?
> > >
> > > > That means I'll now need to work on those ivshmem net devices.
> > >
> > > If you need ivshmem, then this would be the next step.
> > >
> > > Ralf
> > >
> > > >
> > > > Thanks,
> > > > Michele
> > > >
> > > > Il giorno sabato 13 gennaio 2024 alle 15:13:12 UTC+1 Ralf
> > > Ramsauer ha
> > > > scritto:
> > > >
> > > > Hi,
> > > >
> > > > On 13/01/2024 12:28, Michele Pescapè wrote:
> > > > > Hi,
> > > > >
> > > > > You are right, I got confused about those addresses, my bad. At
> > > > least
> > > > > now I know that config is the correct one and I don't have to
> > > tinker
> > > > > with it.
> > > > > I'm back to a kernel panic from the inmate when booting the
> > cell.
> > > > It's
> > > > > similar to the one I had earlier, not sure yet of what the
> > > > problem may be.
> > > >
> > > > Great, we're a step further.
> > > >
> > > > >
> > > > > Created cell "linux-2"
> > > > > Page pool usage after cell creation: mem 406/32211, remap
> > > > 16392/131072
> > > > > Cell "linux-2" can be loaded
> > > > > CPU 9 received SIPI, vector 100
> > > > > Started cell "linux-2"
> > > > > CPU 8 received SIPI, vector 100
> > > > > No EFI environment detected.
> > > > > early console in extract_kernel
> > > > > input_data: 0x000000000275c308
> > > > > input_len: 0x00000000008b0981
> > > > > output: 0x0000000001000000
> > > > > output_len: 0x0000000001fccb30
> > > > > kernel_total_size: 0x0000000001e28000
> > > > > needed_size: 0x0000000002000000
> > > > > trampoline_32bit: 0x000000000009d000
> > > > >
> > > > > Decompressing Linux... Parsing ELF... done.
> > > > > Booting the kernel.
> > > > > [ 0.000000] Linux version 6.2.0-rc3 (root@mp-LINUX-DESKTOP)
> > > > > (x86_64-buildroot -linux-gnu-gcc.br_real (Buildroot
> > 2023.11)
> > > > > 12.3.0, GNU ld (GNU Binutils) 2.40) # 2 SMP
> > PREEMPT_DYNAMIC
> > > > Fri
> > > > > Jan 12 17:36:57 CET 2024
> > > > > [ 0.000000] Command line: earlyprintk=ttyS0,115200
> > > > > [ 0.000000] KERNEL supported cpus:
> > > > > [ 0.000000] Intel GenuineIntel
> > > > > [ 0.000000] AMD AuthenticAMD
> > > > > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87
> > > > floating
> > > > > point regi sters'
> > > > > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE
> > > > registers'
> > > > > [ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX
> > > > registers'
> > > > > [ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]:
> > > > 256
> > > > > [ 0.000000] x86/fpu: Enabled xstate features 0x7, context
> > size
> > > > is 832
> > > > > bytes, using 'compacted' format.
> > > > > [ 0.000000] signal: max sigframe size: 1360
> > > > > [ 0.000000] BIOS-provided physical RAM map:
> > > > > [ 0.000000] BIOS-e801: [mem
> > > > 0x0000000000000000-0x000000000009efff] usable
> > > >
> > > > Okay, here should be all memory regions listed. My non-root Linux
> > > in my
> > > > Qemu VM, for example, shows here:
> > > >
> > > > [ 0.000000] BIOS-provided physical RAM map:
> > > > [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x00000000000fffff]
> > > > usable
> > > > [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x0000000000100fff]
> > > > reserved
> > > > [ 0.000000] BIOS-e820: [mem 0x0000000000200000-0x00000000048fffff]
> > > > usable
> > > >
> > > > Are you absolutely sure, that you have no further modifications in
> > > > Jailhouse or the Linux loader?
> > > >
> > > > Actually, in your case, there should be e820 as well (instead of
> > > e801).
> > > > Go to the Linux kernel sources, have a look at
> > > > arch/x86/kernel/e820.c:1279
> > > >
> > > > and Jailhouse's jailhouse-cell-linux:638.
> > > >
> > > > jailhouse-cell-linux fills information of all memory regions into
> > > the
> > > > zero page. Would you please instrument code (Linux/Jailhouse)
> > to see
> > > > where those regions are not parsed?
> > > >
> > > > > [ 0.000000] printk: bootconsole [earlyser0] enabled
> > > > > [ 0.000000] NX (Execute Disable) protection: active
> > > > > [ 0.000000] extended physical RAM map:
> > > > > [ 0.000000] reserve setup_data: [mem
> > > > > 0x0000000000000000-0x0000000000001fff] u sable
> > > > > [ 0.000000] reserve setup_data: [mem
> > > > > 0x0000000000002000-0x000000000000212b] u sable
> > > > > [ 0.000000] reserve setup_data: [mem
> > > > > 0x000000000000212c-0x000000000009efff] u sable
> > > > > [ 0.000000] DMI not present or invalid.
> > > > > [ 0.000000] Hypervisor detected: Jailhouse
> > > >
> > > > Just guessing loud: Hmm, you have guest support enabled, that's
> > > not the
> > > > issue.
> > > >
> > > > > [ 0.000000] tsc: Detected 3393.624 MHz processor
> > > > > [ 0.000017] .text .data .bss are not marked as E820_TYPE_RAM!
> > > >
> > > > Here's the next error that makes me curious, why you system falls
> > > back
> > > > to E801...
> > > >
> > > > > [ 0.005745] last_pfn = 0x2e28 max_arch_pfn = 0x400000000
> > > > > [ 0.011025] x86/PAT: PAT support disabled because
> > > > CONFIG_X86_PAT is
> > > > > disabled in the kernel.
> > > >
> > > > Please enable CONFIG_X86_PAT and MTRR in your kernel.
> > > >
> > > > > [ 0.019362] x86/PAT: Configuration [0-7]: WB WT UC- UC WB
> > > > WT UC- UC
> > > > > [ 0.034867] Using GB pages for direct mapping
> > > > > [ 0.039193] Kernel panic - not syncing: alloc_low_pages: can
> > > not
> > > > > alloc memory
> > > >
> > > > Yeah, that's the logical aftereffect after the errors above.
> > > >
> > > > Thanks,
> > > > Ralf
> > > >
> > > > > [ 0.046183] CPU: 0 PID: 0 Comm: swapper Not tainted
> > > 6.2.0-rc3 #2
> > > > > [ 0.052176] Call Trace:
> > > > > [ 0.054606] <TASK>
> > > > > [ 0.056691] ? dump_stack_lvl+0x33/0x4e
> > > > > [ 0.060510] ? panic+0x157/0x303
> > > > > [ 0.063723] ? sprintf+0x56/0x80
> > > > > [ 0.066936] ? alloc_low_pages+0x70/0x1a0
> > > > > [ 0.070930] ? phys_pmd_init+0x1fc/0x2eb
> > > > > [ 0.074839] ? phys_pud_init+0x116/0x2d3
> > > > > [ 0.078744] ? __kernel_physical_mapping_init+0x11a/0x290
> > > > > [ 0.084128] ? init_memory_mapping+0x25e/0x3b0
> > > > > [ 0.088558] ? init_range_memory_mapping+0xe7/0x145
> > > > > [ 0.093417] ? init_mem_mapping+0x242/0x298
> > > > > [ 0.097585] ? setup_arch+0x74e/0xcbd
> > > > > [ 0.101231] ? start_kernel+0x66/0x8b7
> > > > > [ 0.104965] ? load_ucode_bsp+0x43/0x11b
> > > > > [ 0.108873] ? secondary_startup_64_no_verify+0xe0/0xeb
> > > > > [ 0.114085] </TASK>
> > > > > [ 0.116255] ---[ end Kernel panic - not syncing:
> > > > alloc_low_pages: can
> > > > > not all oc memory ]---
> > > > >
> > > > >
> > > > > Thank you for your continuous support,
> > > > > Michele
> > > > >
> > > > > Il giorno sabato 13 gennaio 2024 alle 00:05:43 UTC+1 Ralf
> > > > Ramsauer ha
> > > > > scritto:
> > > > >
> > > > > Hi Michele,
> > > > >
> > > > > On 12/01/2024 14:07, Michele Pescapè wrote:
> > > > > > jailhouse cell load linux-2 linux-loader.bin -a 0x0
> > > > > > ../buildroot-2023.11/output/images/bzImage -a 0xffbe00
> > > parameters
> > > > > -a 0x1000
> > > > > > jailhouse cell start linux-2
> > > > > >
> > > > > > I take it the kernel is loaded at 0xffbe00 which is right
> > at the
> > > > > edge of
> > > > > > the low ram region. In fact after issuing the cell load
> > command
> > > > and
> > > > > > adjusting the path for the loader I get JAILHOUSE_CELL_LOAD:
> > > > Invalid
> > > > > > argument.
> > > > >
> > > > > Just tested cell-linux in a qemu machine, there it works, with
> > > > pretty
> > > > > similar addresses, which got me confused.
> > > > >
> > > > > After double-checking it: 0xffb.e00 is *not* at the edge of low
> > > mem:
> > > > >
> > > > > Low mem is 0x000.000 -- 0x0ff.fff
> > > > > Comm region is 0x100.000 -- 0x100.fff
> > > > >
> > > > > 0xffb.e00 is (obviously) way above.
> > > > >
> > > > > Please try to set your high mem's .virt_start to 0x200000. Then,
> > > > > 0xffbe00 is offsetted ~16MB inside your highmem, and it should
> > > work!
> > > > >
> > > > > IOW:
> > > > >
> > > > > /* high RAM */
> > > > > {
> > > > > .phys_start = 0x42300000,
> > > > > .virt_start = 0x200000,
> > > > > .size = 0x11000000,
> > > > > .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
> > > > > JAILHOUSE_MEM_EXECUTE |
> > > > > JAILHOUSE_MEM_LOADABLE,
> > > > > },
> > > > >
> > > > > Thanks
> > > > > Ralf
> > > > >
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/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for Linux inmate, 1 CPU, 74 MB RAM, ~1MB shmem, serial ports
*
* Copyright (c) Siemens AG, 2013-2015
*
* Authors:
* Jan Kiszka <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[7];
struct jailhouse_irqchip irqchips[1];
struct jailhouse_pci_device pci_devices[1];
struct jailhouse_pio pio_regions[3];
struct jailhouse_pci_capability pci_caps[0];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.architecture = JAILHOUSE_X86,
.name = "linux-1",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG |
JAILHOUSE_CELL_VIRTUAL_CONSOLE_PERMITTED,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_caps = ARRAY_SIZE(config.pci_caps),
.console = {
.address = 0x3f8,
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO,
},
},
.cpus = {
0b1100000000,
},
.mem_regions = {
/* IVSHMEM shared memory regions (networking) */
JAILHOUSE_SHMEM_NET_REGIONS(0x60000000, 1),
/* low RAM */
{
.phys_start = 0x3a600000,
.virt_start = 0,
.size = 0x00100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
JAILHOUSE_MEM_LOADABLE,
},
/* communication region */
{
.virt_start = 0x00100000,
.size = 0x00001000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_COMM_REGION,
},
/* high RAM */
{
.phys_start = 0x3a800000,
.virt_start = 0x00200000,
.size = 0x8000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA |
JAILHOUSE_MEM_LOADABLE,
},
},
.irqchips = {
/* IOAPIC 13, GSI base 0 */
{
.address = 0xfec00000,
.id = 0xa0,
.pin_bitmap = {
(1 << 4),
},
},
},
.pio_regions = {
/*Port I/O: serial 1 */
PIO_RANGE(0x3f8, 0x8),
/*Port for pio write on 4e and 4f error on boot*/
PIO_RANGE(0x4e,0x2),
PIO_RANGE(0x2e,0x2),
},
.pci_devices = {
/* IVSHMEM: 00:05.0 */
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.domain = 0x0,
.bdf = 0x28,
.bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
.num_msix_vectors = 2,
.shmem_regions_start = 0,
.shmem_dev_id = 1,
.shmem_peers = 2,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
},
},
};
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2014-2017
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Alternatively, you can use or redistribute this file under the following
* BSD license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* Configuration for Gigabyte Technology Co., Ltd. B450 AORUS M
* created with '/usr/local/libexec/jailhouse/jailhouse config create new_root.c'
*
* NOTE: This config expects the following to be appended to your kernel cmdline
* "memmap=0x68000000$0x3a000000"
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[43];
struct jailhouse_irqchip irqchips[2];
struct jailhouse_pio pio_regions[10];
struct jailhouse_pci_device pci_devices[37];
struct jailhouse_pci_capability pci_caps[105];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.flags = JAILHOUSE_SYS_VIRTUAL_DEBUG_CONSOLE,
.hypervisor_memory = {
.phys_start = 0x3a000000,
.size = 0x600000,
},
.debug_console = {
.address = 0x3f8,
.type = JAILHOUSE_CON_TYPE_8250,
.flags = JAILHOUSE_CON_ACCESS_PIO |
JAILHOUSE_CON_REGDIST_1,
},
.platform_info = {
.pci_mmconfig_base = 0xf8000000,
.pci_mmconfig_end_bus = 0x3f,
/*.iommu_units = {
{
.type = JAILHOUSE_IOMMU_AMD,
.base = 0xfeb80000,
.size = 0x80000,
.amd.bdf = 0x2,
.amd.base_cap = 0x40,
.amd.msi_cap = 0x64,
.amd.features = 0x80048f6f,
},
},*/
.x86 = {
.pm_timer_address = 0x808,
.vtd_interrupt_limit = 256,
},
},
.root_cell = {
.name = "RootCell",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pio_regions = ARRAY_SIZE(config.pio_regions),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.num_pci_caps = ARRAY_SIZE(config.pci_caps),
},
},
.cpus = {
0x0000000000000fff,
},
.mem_regions = {
/* IVSHMEM shared memory regions (networking) */
JAILHOUSE_SHMEM_NET_REGIONS(0x60000000, 0),
/* MemRegion: 0x3a600000-5fffffff : JAILHOUSE Inmate Memory */
{
.phys_start = 0x3a600000,
.virt_start = 0x3a600000,
.size = 0x25a00000,
//.size = 0x20000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE|
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 00000000-0009ffff : System RAM */
{
.phys_start = 0x0,
.virt_start = 0x0,
.size = 0xa0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 000a0000-000dffff : PCI Bus 0000:00 */
{
.phys_start = 0xa0000,
.virt_start = 0xa0000,
.size = 0x40000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 000f0000-000fffff : System ROM */
{
.phys_start = 0xf0000,
.virt_start = 0xf0000,
.size = 0x10000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 00100000-09dfffff : System RAM */
{
.phys_start = 0x100000,
.virt_start = 0x100000,
.size = 0x9d00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 0a000000-0a1fffff : System RAM */
{
.phys_start = 0xa000000,
.virt_start = 0xa000000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 0a200000-0a20afff : ACPI Non-volatile Storage */
{
.phys_start = 0xa200000,
.virt_start = 0xa200000,
.size = 0xb000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 0a20b000-0affffff : System RAM */
{
.phys_start = 0xa20b000,
.virt_start = 0xa20b000,
.size = 0xdf5000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: 0b020000-39ffffff : System RAM */
{
.phys_start = 0xb020000,
.virt_start = 0xb020000,
.size = 0x2efe0000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: a2000000-d887bfff : System RAM */
{
.phys_start = 0xa2000000,
.virt_start = 0xa2000000,
.size = 0x3687c000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: d88d3000-da27efff : System RAM */
{
.phys_start = 0xd88d3000,
.virt_start = 0xd88d3000,
.size = 0x19ac000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: da280000-db9f4fff : System RAM */
{
.phys_start = 0xda280000,
.virt_start = 0xda280000,
.size = 0x1775000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: dbb53000-dbbcffff : ACPI Tables */
{
.phys_start = 0xdbb53000,
.virt_start = 0xdbb53000,
.size = 0x7d000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: dbbd0000-dc12bfff : ACPI Non-volatile Storage */
{
.phys_start = 0xdbbd0000,
.virt_start = 0xdbbd0000,
.size = 0x55c000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: dcd80000-deffffff : System RAM */
{
.phys_start = 0xdcd80000,
.virt_start = 0xdcd80000,
.size = 0x2280000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* MemRegion: e0000000-efffffff : 0000:06:00.0 */
{
.phys_start = 0xe0000000,
.virt_start = 0xe0000000,
.size = 0x10000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: f0000000-f01fffff : 0000:06:00.0 */
{
.phys_start = 0xf0000000,
.virt_start = 0xf0000000,
.size = 0x200000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fc900000-fc9fdfff : xhci-hcd */
{
.phys_start = 0xfc900000,
.virt_start = 0xfc900000,
.size = 0xfe000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fc9ff000-fc9fffff : xhci-hcd */
{
.phys_start = 0xfc9ff000,
.virt_start = 0xfc9ff000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fca00000-fcafffff : ccp */
{
.phys_start = 0xfca00000,
.virt_start = 0xfca00000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcb01000-fcb01fff : ccp */
{
.phys_start = 0xfcb01000,
.virt_start = 0xfcb01000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcc01000-fcc03fff : 0000:03:00.0 */
{
.phys_start = 0xfcc01000,
.virt_start = 0xfcc01000,
.size = 0x3000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcc04000-fcc04fff : r8169 */
{
.phys_start = 0xfcc04000,
.virt_start = 0xfcc04000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcd00000-fcd7ffff : 0000:01:00.1 */
{
.phys_start = 0xfcd00000,
.virt_start = 0xfcd00000,
.size = 0x80000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcd80000-fcd9ffff : ahci */
{
.phys_start = 0xfcd80000,
.virt_start = 0xfcd80000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcda0000-fcda1fff : xhci-hcd */
{
.phys_start = 0xfcda0000,
.virt_start = 0xfcda0000,
.size = 0x2000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcda3000-fcda7fff : xhci-hcd */
{
.phys_start = 0xfcda3000,
.virt_start = 0xfcda3000,
.size = 0x5000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fce00000-fce07fff : ICH HD audio */
{
.phys_start = 0xfce00000,
.virt_start = 0xfce00000,
.size = 0x8000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fce08000-fce08fff : ahci */
{
.phys_start = 0xfce08000,
.virt_start = 0xfce08000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcf00000-fcf3ffff : 0000:06:00.0 */
{
.phys_start = 0xfcf00000,
.virt_start = 0xfcf00000,
.size = 0x40000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcf40000-fcf5ffff : 0000:06:00.0 */
{
.phys_start = 0xfcf40000,
.virt_start = 0xfcf40000,
.size = 0x20000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fcf60000-fcf63fff : ICH HD audio */
{
.phys_start = 0xfcf60000,
.virt_start = 0xfcf60000,
.size = 0x4000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fec10000-fec10fff : pnp 00:05 */
{
.phys_start = 0xfec10000,
.virt_start = 0xfec10000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fec30000-fec30fff : AMDIF030:00 AMDIF030:00 */
{
.phys_start = 0xfec30000,
.virt_start = 0xfec30000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed00000-fed003ff : PNP0103:00 */
{
.phys_start = 0xfed00000,
.virt_start = 0xfed00000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fed81500-fed818ff : AMDI0030:00 AMDI0030:00 */
{
.phys_start = 0xfed81500,
.virt_start = 0xfed81500,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: fedc0000-fedc0fff : pnp 00:05 */
{
.phys_start = 0xfedc0000,
.virt_start = 0xfedc0000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: ff000000-ffffffff : pnp 00:05 */
{
.phys_start = 0xff000000,
.virt_start = 0xff000000,
.size = 0x1000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* MemRegion: 100000000-41fffffff : System RAM */
{
.phys_start = 0x100000000,
.virt_start = 0x100000000,
.size = 0x320000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA,
},
/* : 3a600000-3f1fffff : JAILHOUSE Inmate Memory */
/* {
.phys_start = 0x3a600000,
.virt_start = 0x3a600000,
.size = 0x4c00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},*/
},
.irqchips = {
/* IOAPIC 13, GSI base 0 */
{
.address = 0xfec00000,
.id = 0xa0,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
/* IOAPIC 14, GSI base 24 */
{
.address = 0xfec01000,
.id = 0x1,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff
},
},
},
.pio_regions = {
/* Port I/O: 0000-001f : dma1 */
/* PIO_RANGE(0x0, 0x20), */
/* Port I/O: 0020-0021 : pic1 */
/* PIO_RANGE(0x20, 0x2), */
/* Port I/O: 0040-0043 : timer0 */
PIO_RANGE(0x40, 0x4),
/* Port I/O: 0050-0053 : timer1 */
/* PIO_RANGE(0x50, 0x4), */
/* Port I/O: 0060-0060 : keyboard */
PIO_RANGE(0x60, 0x1),
/* Port I/O: 0061-0061 : PNP0800:00 */
PIO_RANGE(0x61, 0x1),
/* Port I/O: 0064-0064 : keyboard */
PIO_RANGE(0x64, 0x1),
/* Port I/O: 0070-0071 : rtc0 */
PIO_RANGE(0x70, 0x2),
/* Port I/O: 0080-008f : dma page reg */
/* PIO_RANGE(0x80, 0x10), */
/* Port I/O: 00a0-00a1 : pic2 */
/* PIO_RANGE(0xa0, 0x2), */
/* Port I/O: 00c0-00df : dma2 */
/* PIO_RANGE(0xc0, 0x20), */
/* Port I/O: 00f0-00ff : fpu */
/* PIO_RANGE(0xf0, 0x10), */
/* Port I/O: 0378-037a : parport0 */
/* PIO_RANGE(0x378, 0x3), */
/* Port I/O: 037b-037f : parport0 */
/* PIO_RANGE(0x37b, 0x5), */
/* Port I/O: 03b0-03df : PCI Bus 0000:00 */
/* PIO_RANGE(0x3b0, 0x30), */
/* Port I/O: 03f8-03ff : serial */
PIO_RANGE(0x3f8, 0x8),
/* Port I/O: 040b-040b : pnp 00:05 */
/* PIO_RANGE(0x40b, 0x1), */
/* Port I/O: 04d0-04d1 : pnp 00:05 */
/* PIO_RANGE(0x4d0, 0x2), */
/* Port I/O: 04d6-04d6 : pnp 00:05 */
/* PIO_RANGE(0x4d6, 0x1), */
/* Port I/O: 0800-0803 : ACPI PM1a_EVT_BLK */
/* PIO_RANGE(0x800, 0x4), */
/* Port I/O: 0804-0805 : ACPI PM1a_CNT_BLK */
/* PIO_RANGE(0x804, 0x2), */
/* Port I/O: 0808-080b : ACPI PM_TMR */
/* PIO_RANGE(0x808, 0x4), */
/* Port I/O: 0810-0815 : ACPI CPU throttle */
/* PIO_RANGE(0x810, 0x6), */
/* Port I/O: 0820-0827 : ACPI GPE0_BLK */
/* PIO_RANGE(0x820, 0x8), */
/* Port I/O: 0900-090f : pnp 00:05 */
/* PIO_RANGE(0x900, 0x10), */
/* Port I/O: 0910-091f : pnp 00:05 */
/* PIO_RANGE(0x910, 0x10), */
/* Port I/O: 0a00-0a2f : pnp 00:02 */
/* PIO_RANGE(0xa00, 0x30), */
/* Port I/O: 0a30-0a3f : pnp 00:02 */
/* PIO_RANGE(0xa30, 0x10), */
/* Port I/O: 0a40-0a4f : pnp 00:02 */
/* PIO_RANGE(0xa40, 0x10), */
/* Port I/O: 0b00-0b08 : piix4_smbus */
/* PIO_RANGE(0xb00, 0x9), */
/* Port I/O: 0b20-0b28 : piix4_smbus */
/* PIO_RANGE(0xb20, 0x9), */
/* Port I/O: 0c00-0c01 : pnp 00:05 */
/* PIO_RANGE(0xc00, 0x2), */
/* Port I/O: 0c14-0c14 : pnp 00:05 */
/* PIO_RANGE(0xc14, 0x1), */
/* Port I/O: 0c50-0c51 : pnp 00:05 */
/* PIO_RANGE(0xc50, 0x2), */
/* Port I/O: 0c52-0c52 : pnp 00:05 */
/* PIO_RANGE(0xc52, 0x1), */
/* Port I/O: 0c6c-0c6c : pnp 00:05 */
/* PIO_RANGE(0xc6c, 0x1), */
/* Port I/O: 0c6f-0c6f : pnp 00:05 */
/* PIO_RANGE(0xc6f, 0x1), */
/* Port I/O: 0cd0-0cd1 : pnp 00:05 */
/* PIO_RANGE(0xcd0, 0x2), */
/* Port I/O: 0cd2-0cd3 : pnp 00:05 */
/* PIO_RANGE(0xcd2, 0x2), */
/* Port I/O: 0cd4-0cd5 : pnp 00:05 */
/* PIO_RANGE(0xcd4, 0x2), */
/* Port I/O: 0cd6-0cd7 : pnp 00:05 */
/* PIO_RANGE(0xcd6, 0x2), */
/* Port I/O: 0cd8-0cdf : pnp 00:05 */
/* PIO_RANGE(0xcd8, 0x8), */
/* Port I/O: e000-e0ff : 0000:06:00.0 */
PIO_RANGE(0xe000, 0x100),
/* Port I/O: f000-f0ff : 0000:03:00.0 */
PIO_RANGE(0xf000, 0x100),
//pio range for invalid pio read, port 414 size 1
PIO_RANGE(0x414, 0x1),
PIO_RANGE(0x810, 0x4),
},
.pci_devices = {
/* IVSHMEM: 00:05.0 - guest 1*/
{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.domain = 0x0,
.bdf = 0x28,
.bar_mask = JAILHOUSE_IVSHMEM_BAR_MASK_MSIX,
.num_msix_vectors = 2,
.shmem_regions_start = 0,
.shmem_dev_id = 0,
.shmem_peers = 2,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH,
},
/* PCIDevice: 00:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.domain = 0x0,
.bdf = 0x0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x8,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:01.3 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xb,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 11,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:02.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x10,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:03.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x18,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:03.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x19,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 11,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x20,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:07.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x38,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:07.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x39,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 11,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:08.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x40,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:08.1 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x41,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 11,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xa0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:14.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xa3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc0,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc1,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc2,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc3,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.4 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc4,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.5 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc5,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.6 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc6,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 00:18.7 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0xc7,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 0,
.num_caps = 0,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 01:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x100,
.bar_mask = {
0xffff8000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 20,
.num_caps = 8,
.num_msi_vectors = 8,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 8,
.msix_region_size = 0x1000,
.msix_address = 0xfcda2000,
},
/* PCIDevice: 01:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x101,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfffe0000,
},
.caps_start = 28,
.num_caps = 4,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 01:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x102,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 32,
.num_caps = 5,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 02:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x200,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 37,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 02:01.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x208,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 37,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 02:04.0 */
{
.type = JAILHOUSE_PCI_TYPE_BRIDGE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x220,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 37,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 03:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x300,
.bar_mask = {
0xffffff00, 0x00000000, 0xfffff000,
0xffffffff, 0xffffc000, 0xffffffff,
},
.caps_start = 44,
.num_caps = 9,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 4,
.msix_region_size = 0x1000,
.msix_address = 0xfcc00000,
},
/* PCIDevice: 06:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x600,
.bar_mask = {
0xf0000000, 0xffffffff, 0xffe00000,
0xffffffff, 0xffffff00, 0xfffc0000,
},
.caps_start = 53,
.num_caps = 14,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 06:00.1 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x601,
.bar_mask = {
0xffffc000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 67,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 07:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x700,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 74,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 07:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x702,
.bar_mask = {
0x00000000, 0x00000000, 0xfff00000,
0x00000000, 0x00000000, 0xffffe000,
},
.caps_start = 81,
.num_caps = 8,
.num_msi_vectors = 2,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 2,
.msix_region_size = 0x1000,
.msix_address = 0xfcb00000,
},
/* PCIDevice: 07:00.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x703,
.bar_mask = {
0xfff00000, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 81,
.num_caps = 8,
.num_msi_vectors = 8,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 8,
.msix_region_size = 0x1000,
.msix_address = 0xfc9fe000,
},
/* PCIDevice: 08:00.0 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x800,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 74,
.num_caps = 7,
.num_msi_vectors = 0,
.msi_64bits = 0,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 08:00.2 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x802,
.bar_mask = {
0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0xfffff000,
},
.caps_start = 89,
.num_caps = 8,
.num_msi_vectors = 16,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
/* PCIDevice: 08:00.3 */
{
.type = JAILHOUSE_PCI_TYPE_DEVICE,
.iommu = 0,
.domain = 0x0,
.bdf = 0x803,
.bar_mask = {
0xffff8000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.caps_start = 97,
.num_caps = 7,
.num_msi_vectors = 1,
.msi_64bits = 1,
.msi_maskable = 0,
.num_msix_vectors = 0,
.msix_region_size = 0x0,
.msix_address = 0x0,
},
},
.pci_caps = {
/* PCIDevice: 00:01.3 */
/* PCIDevice: 00:03.1 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_HT,
.start = 0xc8,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x370,
.len = 0x4,
.flags = 0,
},
{
.id = 0x23 | JAILHOUSE_PCI_EXT_CAP,
.start = 0x3c4,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 00:07.1 */
/* PCIDevice: 00:08.1 */
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_HT,
.start = 0xc8,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 01:00.0 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0x68,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x300,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x400,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 01:00.1 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
/* PCIDevice: 01:00.2 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
/* PCIDevice: 02:00.0 */
/* PCIDevice: 02:01.0 */
/* PCIDevice: 02:04.0 */
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x78,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x80,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_SSVID,
.start = 0xc0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x400,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 03:00.0 */
{
.id = PCI_CAP_ID_PM,
.start = 0x40,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0x50,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x70,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xb0,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VC | JAILHOUSE_PCI_EXT_CAP,
.start = 0x140,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_DSN | JAILHOUSE_PCI_EXT_CAP,
.start = 0x160,
.len = 0xc,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x170,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x178,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 06:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_REBAR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x200,
.len = 0x4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ATS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2b0,
.len = 0x4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PRI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2c0,
.len = 0x4,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_PASID | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2d0,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_LTR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x320,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ARI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x328,
.len = 0x8,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_L1SS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x370,
.len = 0x4,
.flags = 0,
},
/* PCIDevice: 06:00.1 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x58,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ARI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x328,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 07:00.0 */
/* PCIDevice: 08:00.0 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_SECPCI | JAILHOUSE_PCI_EXT_CAP,
.start = 0x270,
.len = 0x10,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 07:00.2 */
/* PCIDevice: 07:00.3 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSIX,
.start = 0xc0,
.len = 0xc,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 08:00.2 */
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = 0,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_SATA,
.start = 0xd0,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x8,
.flags = 0,
},
/* PCIDevice: 08:00.3 */
{
//.id = PCI_CAP_ID_VNDR,
.start = 0x42,
.len = 0x1,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_VNDR,
.start = 0x48,
.len = 0x2,
.flags = 0,
},
{
.id = PCI_CAP_ID_PM,
.start = 0x50,
.len = 0x8,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_EXP,
.start = 0x64,
.len = 0x3c,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_CAP_ID_MSI,
.start = 0xa0,
.len = 0xe,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_VNDR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x100,
.len = 0x14,
.flags = 0,
},
{
.id = PCI_EXT_CAP_ID_ERR | JAILHOUSE_PCI_EXT_CAP,
.start = 0x150,
.len = 0x40,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
{
.id = PCI_EXT_CAP_ID_ACS | JAILHOUSE_PCI_EXT_CAP,
.start = 0x2a0,
.len = 0x9,
.flags = JAILHOUSE_PCICAPS_WRITE,
},
},
};
