Revision: 1126 Author: robhamerling Date: Sun Jul 26 23:55:39 2009 Log: update for changes in device files
http://code.google.com/p/jallib/source/detail?r=1126 Modified: /trunk/CHANGELOG ======================================= --- /trunk/CHANGELOG Sun Jul 26 14:57:13 2009 +++ /trunk/CHANGELOG Sun Jul 26 23:55:39 2009 @@ -2,30 +2,36 @@ ----------- device files: - - Based on MPlab version 8.33, new device files for: + - based on MPLAB version 8.33, new device files for 12F520, 18F66J93, 18F67J93, 18F86J93, 18F87J93, 18F87K22, 18F87K90. - - Added pin-aliases with the help of contents /tools/pinmap.py file. - - Normalized ANSx subfields of ANSELx and ADCONx to JANSEL_ANSx naming. - - Added enumeration of bitfield VCFG of ADCON0 and ADCON1. - - ADCONx_[P]VCFG now both as multi-bit field as enumerated bits. - - ANSEL of 12F609, 12HV609, 16F610, and 16HV610 rehabilitated. - These chips have no ADC, but do have an analog comparator! - - Fix for declaration of SFRs of 18Fs: only SFRs above - 0xF00+AccessBankSplitOffset are declared 'shared'. - - Several corrections for 12F519: PORTB -> GPIO/PORTA, TRISB -> TRISIO, - controlling T0CS bit in enable_digital_io(), flash-data -> EEPROM. - - Added pseudo variable ADCON0_CHS for 16F7x7 with 'splitted' CHS bits. - - Added declaration for pin_A3,1,0 to 18F13/14K50 and their LF variants. - - Removed fuse_def statements for ENICPORT and for some unsupported bits - of the 18Fs (protection bits of not present code/data/write memory). - - Added: const byte ADC_NTOTAL_CHANNEL = <number> (of ADC channels) - - Revised fuse_def OSC: now handled by table. - - Minor changes in output formatting (for html doc generation). + - added: + + pin-aliases with help of /tools/pinmap_pinsuffix.json. + + enumeration of bitfield VCFG of ADCON0 and ADCON1 registers + + const byte ADC_NTOTAL_CHANNEL = <#> (number of of ADC channels), + + const byte[] PICTYPE, DATASHEET and PGMSPEC (without letter suffixes) + + const word DEVICE_ID + + pseudo variable ADCON0_CHS for 16F7x7 with 'splitted' CHS bits. + + declaration for pin_A3,1,0 to 18F13/14K50 and their LF variants. + - removed: + - fuse_def statements for ENICPORT and for some unsupported bits + of the 18Fs (protection bits of not present code/data/write memory). + - fixed: + * declaration of SFRs of 18Fs: only SFRs above + 0xF00+AccessBankSplitOffset are declared 'shared'. + * 12F519: registers renamed: PORTB -> GPIO/PORTA, TRISB -> TRISIO; + T0CS bit setting added to enable_digital_io(), flash-data -> EEPROM. + * ANSEL of 12F609, 12HV609, 16F610, and 16HV610 rehabilitated + (these chips have no ADC, but do have an analog comparator). + - other changes: + * normalized ANSx subfields of ANSELx and ADCONx to JANSEL_ANSx naming. + * ADCONx_[P]VCFG now both declared as multi-bit field and as enumerated bits. + * fuse_def OSC now handled by table (/tools/fusedefmap.cmd) + * minor changes in output formatting (for html doc generation). externals: - Added: Backlight API for LCD backlight on/off or pwm - - Keyboard updated: new one-shot function getkey_once() and configuration of + - Keyboard updated: new one-shot function getkey_once() and configuration of used pins without modification of the library peripherals: --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/jallib?hl=en -~----------~----~----~----~------~----~------~--~---
