Revision: 1132 Author: [email protected] Date: Fri Jul 31 13:18:04 2009 Log: Fixed Issue 70: Added (E)CCPXCON aliases, added newly generated PWM related samples http://code.google.com/p/jallib/source/detail?r=1132
Added: /trunk/sample/18f14k50_pwm_led.jal /trunk/sample/18f14k50_pwm_led_highres.jal /trunk/sample/18f14k50_pwm_sound.jal /trunk/sample/18f4550_pwm_led.jal /trunk/sample/18f4550_pwm_led_highres.jal /trunk/sample/18f4550_pwm_sound.jal Modified: /trunk/include/peripheral/pwm/pwm_hardware.jal /trunk/project/pic18f14k50_usb_io/examples/usb_i2c_master.jal /trunk/sample/18f14k50_usb_bootloader.jal /trunk/sample/18f2450_pwm_led.jal /trunk/sample/18f2450_pwm_led_highres.jal /trunk/sample/18f2450_pwm_sound.jal /trunk/sample/18f2450_usb_bootloader.jal /trunk/test/board/board_18f14k50_af.jal /trunk/test/board/board_18f2450_af.jal /trunk/test/board/board_18f4550_af.jal ======================================= --- /dev/null +++ /trunk/sample/18f14k50_pwm_led.jal Fri Jul 31 13:18:04 2009 @@ -0,0 +1,98 @@ +-- Title: Test program for 1 PWM channel, using a LED +-- Author: Sebastien Lelong, Copyright (c) 2008-2009, all rights reserved. +-- Adapted-by: +-- Compiler: >=2.4i +-- +-- This file is part of jallib (http://jallib.googlecode.com) +-- Released under the BSD license (http://www.opensource.org/licenses/bsd-license.php) +-- +-- Description: this sample show how to use PWM in low resolution mode. +-- It progressively light up and down a LED. Sweet... +-- +-- +-- +-- +-- This file has been generated from: +-- * board: board_18f14k50_af.jal +-- * test : test_pwm_led.jal +-- + +;@jallib section chipdef +-- chip setup +include 18f14k50 + +-- This file is the setup for my homebrew, 18f14k50 board +-- Currently it is a bare board, with just a PIC and a couple of headers +-- A 12 MHz external crystal and 15pf caps connected to OSC1/2 +-- pin 17 (Vusb) with a 220 nF capacitor to the ground +-- The connection between PC and the 18F14k50 +-- +5v to power the board (don't forget 100nf decoupling cap +-- data- wire to pin 18 (D-) +-- data+ wire to pin 19 (D+) +-- ground wire to the Vss of the PIC +-- even though the external crystal is 12 MHz, the configuration is such that +-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set +-- target frequency to 48 MHz +pragma target clock 48_000_000 + + +-- fuses +pragma target CPUDIV NO_CPU_SYSTEM_CLOCK_DIVIDE +pragma target USBDIV USB_CLOCK_COMES_DIRECTLY_FROM_THE_OSC1_OSC2_OSCILLATOR_BLOCK__NO_DIVIDE +pragma target OSC HS +pragma target PLLEN OSCILLATOR_MULTIPLIED_BY_4 +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target VOLTAGE V30 -- brown out voltage +pragma target WDT DISABLED -- no watchdog +pragma target WDTPS P32768 -- watch dog saler setting +pragma target MCLR INTERNAL -- no master reset +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTRB DISABLED -- boot block not protected +pragma target HFOFST THE_SYSTEM_CLOCK_IS_HELD_OFF_UNTIL_THE_HFINTOSC_IS_STABLE + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + +enable_digital_io() + +-- Configure PWM +pin_ccp1_direction = output +include pwm_hardware +pwm_max_resolution(1) +pwm1_on() + +forever loop + var byte i + i = 0 + -- loop up and down, to produce different duty cycle + while i < 250 loop + pwm1_set_dutycycle(i) + _usec_delay(10000) + i = i + 1 + end loop + while i > 0 loop + pwm1_set_dutycycle(i) + _usec_delay(10000) + i = i - 1 + end loop + -- turning off, the LED lights at max. + _usec_delay(500000) + pwm1_off() + _usec_delay(500000) + pwm1_on() + +end loop ======================================= --- /dev/null +++ /trunk/sample/18f14k50_pwm_led_highres.jal Fri Jul 31 13:18:04 2009 @@ -0,0 +1,100 @@ +-- Title: Test program for hardware (built-in) PWM, in high resolution mode, using a LED +-- Author: Sebastien Lelong, Copyright (c) 2008-2009, all rights reserved. +-- Adapted-by: +-- Compiler: >=2.4i +-- +-- This file is part of jallib (http://jallib.googlecode.com) +-- Released under the BSD license (http://www.opensource.org/licenses/bsd-license.php) +-- +-- Description: this sample shows how to use PWM in high resolution mode +-- It lights up and down an LED. +-- +-- +-- +-- This file has been generated from: +-- * board: board_18f14k50_af.jal +-- * test : test_pwm_led_highres.jal +-- + +;@jallib section chipdef +-- chip setup +include 18f14k50 + +-- This file is the setup for my homebrew, 18f14k50 board +-- Currently it is a bare board, with just a PIC and a couple of headers +-- A 12 MHz external crystal and 15pf caps connected to OSC1/2 +-- pin 17 (Vusb) with a 220 nF capacitor to the ground +-- The connection between PC and the 18F14k50 +-- +5v to power the board (don't forget 100nf decoupling cap +-- data- wire to pin 18 (D-) +-- data+ wire to pin 19 (D+) +-- ground wire to the Vss of the PIC +-- even though the external crystal is 12 MHz, the configuration is such that +-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set +-- target frequency to 48 MHz +pragma target clock 48_000_000 + + +-- fuses +pragma target CPUDIV NO_CPU_SYSTEM_CLOCK_DIVIDE +pragma target USBDIV USB_CLOCK_COMES_DIRECTLY_FROM_THE_OSC1_OSC2_OSCILLATOR_BLOCK__NO_DIVIDE +pragma target OSC HS +pragma target PLLEN OSCILLATOR_MULTIPLIED_BY_4 +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target VOLTAGE V30 -- brown out voltage +pragma target WDT DISABLED -- no watchdog +pragma target WDTPS P32768 -- watch dog saler setting +pragma target MCLR INTERNAL -- no master reset +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTRB DISABLED -- boot block not protected +pragma target HFOFST THE_SYSTEM_CLOCK_IS_HELD_OFF_UNTIL_THE_HFINTOSC_IS_STABLE + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + +enable_digital_io() + +-- Configure PWM +pin_ccp1_direction = output +include pwm_hardware +pwm_max_resolution(1) +pwm1_on() + + +forever loop + + var word i + i = 0 + + -- High resolution means up to 10bits values (duty < 1024) + while i < 1020 loop + pwm1_set_dutycycle_highres(i) + _usec_delay(50000) + i = i + 10 + end loop + while i > 0 loop + pwm1_set_dutycycle_highres(i) + _usec_delay(50000) + i = i - 10 + end loop + + _usec_delay(500000) + pwm1_off() + _usec_delay(500000) + pwm1_on() + +end loop ======================================= --- /dev/null +++ /trunk/sample/18f14k50_pwm_sound.jal Fri Jul 31 13:18:04 2009 @@ -0,0 +1,93 @@ +-- Title: Test program for hardware (built-in) PWM. Plays sound +-- Author: Sebastien Lelong, Copyright (c) 2008, all rights reserved. +-- Adapted-by: +-- Compiler: >=2.4i +-- +-- This file is part of jallib (http://jallib.googlecode.com) +-- Released under the BSD license (http://www.opensource.org/licenses/bsd-license.php) +-- +-- Description: this sample show how to use PWM with a constant duty cycle and +-- a variable frequency. It plays a "nice" melody (connect a small piezzo) +-- Frequencies from 0 to 100_000Hz are played. At the beginning, no sound will come +-- the buzzer, because frequency is too low (no valid combination of PR2/T2CON) +-- +-- +-- +-- +-- This file has been generated from: +-- * board: board_18f14k50_af.jal +-- * test : test_pwm_sound.jal +-- + +;@jallib section chipdef +-- chip setup +include 18f14k50 + +-- This file is the setup for my homebrew, 18f14k50 board +-- Currently it is a bare board, with just a PIC and a couple of headers +-- A 12 MHz external crystal and 15pf caps connected to OSC1/2 +-- pin 17 (Vusb) with a 220 nF capacitor to the ground +-- The connection between PC and the 18F14k50 +-- +5v to power the board (don't forget 100nf decoupling cap +-- data- wire to pin 18 (D-) +-- data+ wire to pin 19 (D+) +-- ground wire to the Vss of the PIC +-- even though the external crystal is 12 MHz, the configuration is such that +-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set +-- target frequency to 48 MHz +pragma target clock 48_000_000 + + +-- fuses +pragma target CPUDIV NO_CPU_SYSTEM_CLOCK_DIVIDE +pragma target USBDIV USB_CLOCK_COMES_DIRECTLY_FROM_THE_OSC1_OSC2_OSCILLATOR_BLOCK__NO_DIVIDE +pragma target OSC HS +pragma target PLLEN OSCILLATOR_MULTIPLIED_BY_4 +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target VOLTAGE V30 -- brown out voltage +pragma target WDT DISABLED -- no watchdog +pragma target WDTPS P32768 -- watch dog saler setting +pragma target MCLR INTERNAL -- no master reset +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTRB DISABLED -- boot block not protected +pragma target HFOFST THE_SYSTEM_CLOCK_IS_HELD_OFF_UNTIL_THE_HFINTOSC_IS_STABLE + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + +enable_digital_io() + +-- Configure PWM +pin_ccp1_direction = output +include pwm_hardware +-- Let's go !!! +pwm1_on() + + +var dword counter = 0 +forever loop + + for 100_000 using counter loop + pwm_set_frequency(counter) + -- Setting @50% gives max volume + -- must be re-computed each time the frequency + -- changes, because it depends on PR2 value + pwm1_set_percent_dutycycle(50) + end loop + +end loop + ======================================= --- /dev/null +++ /trunk/sample/18f4550_pwm_led.jal Fri Jul 31 13:18:04 2009 @@ -0,0 +1,101 @@ +-- Title: Test program for 1 PWM channel, using a LED +-- Author: Sebastien Lelong, Copyright (c) 2008-2009, all rights reserved. +-- Adapted-by: +-- Compiler: >=2.4i +-- +-- This file is part of jallib (http://jallib.googlecode.com) +-- Released under the BSD license (http://www.opensource.org/licenses/bsd-license.php) +-- +-- Description: this sample show how to use PWM in low resolution mode. +-- It progressively light up and down a LED. Sweet... +-- +-- +-- +-- +-- This file has been generated from: +-- * board: board_18f4550_af.jal +-- * test : test_pwm_led.jal +-- + +;@jallib section chipdef +-- chip setup +include 18f4550 + +-- even though the external crystal is 20 MHz, the configuration is such that +-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set +-- target frequency to 48 MHz +pragma target clock 48_000_000 + + +-- fuses +pragma target PLLDIV DIVIDE_BY_5__20MHZ_INPUT_ +pragma target CPUDIV _OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_ +pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 +pragma target OSC HS_PLL +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target VREGEN ENABLED -- USB voltage regulator +pragma target VOLTAGE V20 -- brown out voltage +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target WDTPS P32768 -- watch dog saler setting +pragma target WDT DISABLED -- no watchdog +pragma target CCP2MUX RC1 -- CCP2 pin +pragma target PBADEN DIGITAL -- digital input port<0..4> +pragma target LPT1OSC DISABLED -- low power timer 1 +pragma target MCLR EXTERNAL -- master reset on RE3 +pragma target STVR DISABLED -- reset on stack over/under flow +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CP_2 DISABLED -- code block 2 not protected +pragma target CP_3 DISABLED -- code block 3 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target CPD DISABLED -- eeprom code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRT_2 DISABLED -- table write block 2 not protected +pragma target WRT_3 DISABLED -- table write block 3 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTD DISABLED -- eeprom not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTR_2 DISABLED -- table read block 2 not protected +pragma target EBTR_3 DISABLED -- table read block 3 not protected +pragma target EBTRB DISABLED -- boot block not protected + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + +enable_digital_io() + +-- Configure PWM +pin_ccp1_direction = output +include pwm_hardware +pwm_max_resolution(1) +pwm1_on() + +forever loop + var byte i + i = 0 + -- loop up and down, to produce different duty cycle + while i < 250 loop + pwm1_set_dutycycle(i) + _usec_delay(10000) + i = i + 1 + end loop + while i > 0 loop + pwm1_set_dutycycle(i) + _usec_delay(10000) + i = i - 1 + end loop + -- turning off, the LED lights at max. + _usec_delay(500000) + pwm1_off() + _usec_delay(500000) + pwm1_on() + +end loop ======================================= --- /dev/null +++ /trunk/sample/18f4550_pwm_led_highres.jal Fri Jul 31 13:18:04 2009 @@ -0,0 +1,103 @@ +-- Title: Test program for hardware (built-in) PWM, in high resolution mode, using a LED +-- Author: Sebastien Lelong, Copyright (c) 2008-2009, all rights reserved. +-- Adapted-by: +-- Compiler: >=2.4i +-- +-- This file is part of jallib (http://jallib.googlecode.com) +-- Released under the BSD license (http://www.opensource.org/licenses/bsd-license.php) +-- +-- Description: this sample shows how to use PWM in high resolution mode +-- It lights up and down an LED. +-- +-- +-- +-- This file has been generated from: +-- * board: board_18f4550_af.jal +-- * test : test_pwm_led_highres.jal +-- + +;@jallib section chipdef +-- chip setup +include 18f4550 + +-- even though the external crystal is 20 MHz, the configuration is such that +-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set +-- target frequency to 48 MHz +pragma target clock 48_000_000 + + +-- fuses +pragma target PLLDIV DIVIDE_BY_5__20MHZ_INPUT_ +pragma target CPUDIV _OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_ +pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 +pragma target OSC HS_PLL +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target VREGEN ENABLED -- USB voltage regulator +pragma target VOLTAGE V20 -- brown out voltage +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target WDTPS P32768 -- watch dog saler setting +pragma target WDT DISABLED -- no watchdog +pragma target CCP2MUX RC1 -- CCP2 pin +pragma target PBADEN DIGITAL -- digital input port<0..4> +pragma target LPT1OSC DISABLED -- low power timer 1 +pragma target MCLR EXTERNAL -- master reset on RE3 +pragma target STVR DISABLED -- reset on stack over/under flow +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CP_2 DISABLED -- code block 2 not protected +pragma target CP_3 DISABLED -- code block 3 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target CPD DISABLED -- eeprom code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRT_2 DISABLED -- table write block 2 not protected +pragma target WRT_3 DISABLED -- table write block 3 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTD DISABLED -- eeprom not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTR_2 DISABLED -- table read block 2 not protected +pragma target EBTR_3 DISABLED -- table read block 3 not protected +pragma target EBTRB DISABLED -- boot block not protected + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + +enable_digital_io() + +-- Configure PWM +pin_ccp1_direction = output +include pwm_hardware +pwm_max_resolution(1) +pwm1_on() + + +forever loop + + var word i + i = 0 + + -- High resolution means up to 10bits values (duty < 1024) + while i < 1020 loop + pwm1_set_dutycycle_highres(i) + _usec_delay(50000) + i = i + 10 + end loop + while i > 0 loop + pwm1_set_dutycycle_highres(i) + _usec_delay(50000) + i = i - 10 + end loop + + _usec_delay(500000) + pwm1_off() + _usec_delay(500000) + pwm1_on() + +end loop ======================================= --- /dev/null +++ /trunk/sample/18f4550_pwm_sound.jal Fri Jul 31 13:18:04 2009 @@ -0,0 +1,96 @@ +-- Title: Test program for hardware (built-in) PWM. Plays sound +-- Author: Sebastien Lelong, Copyright (c) 2008, all rights reserved. +-- Adapted-by: +-- Compiler: >=2.4i +-- +-- This file is part of jallib (http://jallib.googlecode.com) +-- Released under the BSD license (http://www.opensource.org/licenses/bsd-license.php) +-- +-- Description: this sample show how to use PWM with a constant duty cycle and +-- a variable frequency. It plays a "nice" melody (connect a small piezzo) +-- Frequencies from 0 to 100_000Hz are played. At the beginning, no sound will come +-- the buzzer, because frequency is too low (no valid combination of PR2/T2CON) +-- +-- +-- +-- +-- This file has been generated from: +-- * board: board_18f4550_af.jal +-- * test : test_pwm_sound.jal +-- + +;@jallib section chipdef +-- chip setup +include 18f4550 + +-- even though the external crystal is 20 MHz, the configuration is such that +-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set +-- target frequency to 48 MHz +pragma target clock 48_000_000 + + +-- fuses +pragma target PLLDIV DIVIDE_BY_5__20MHZ_INPUT_ +pragma target CPUDIV _OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_ +pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 +pragma target OSC HS_PLL +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target VREGEN ENABLED -- USB voltage regulator +pragma target VOLTAGE V20 -- brown out voltage +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target WDTPS P32768 -- watch dog saler setting +pragma target WDT DISABLED -- no watchdog +pragma target CCP2MUX RC1 -- CCP2 pin +pragma target PBADEN DIGITAL -- digital input port<0..4> +pragma target LPT1OSC DISABLED -- low power timer 1 +pragma target MCLR EXTERNAL -- master reset on RE3 +pragma target STVR DISABLED -- reset on stack over/under flow +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CP_2 DISABLED -- code block 2 not protected +pragma target CP_3 DISABLED -- code block 3 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target CPD DISABLED -- eeprom code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRT_2 DISABLED -- table write block 2 not protected +pragma target WRT_3 DISABLED -- table write block 3 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTD DISABLED -- eeprom not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTR_2 DISABLED -- table read block 2 not protected +pragma target EBTR_3 DISABLED -- table read block 3 not protected +pragma target EBTRB DISABLED -- boot block not protected + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + +enable_digital_io() + +-- Configure PWM +pin_ccp1_direction = output +include pwm_hardware +-- Let's go !!! +pwm1_on() + + +var dword counter = 0 +forever loop + + for 100_000 using counter loop + pwm_set_frequency(counter) + -- Setting @50% gives max volume + -- must be re-computed each time the frequency + -- changes, because it depends on PR2 value + pwm1_set_percent_dutycycle(50) + end loop + +end loop + ======================================= --- /trunk/include/peripheral/pwm/pwm_hardware.jal Sat Jan 3 02:06:43 2009 +++ /trunk/include/peripheral/pwm/pwm_hardware.jal Fri Jul 31 13:18:04 2009 @@ -1,6 +1,6 @@ -- Title: hardware PWM control -- Author: Sebastien Lelong, Copyright (C) 2008-2009, all rights reserved. --- Adapted-by: +-- Adapted-by: Albert Faber -- Compiler: >=2.4i -- -- This file is part of jallib (http://jallib.googlecode.com) @@ -24,7 +24,37 @@ -- Notes: this libraries uses conditional compilation. It requires -- at least jalv2 2.4i compiler version -- - + +-- Alias ECCP register for PIC18f devices +if defined( ECCP1CON ) == true then + if defined( CCP1CON ) == false then + var volatile byte CCP1CON is ECCP1CON + end if +end if + +if defined( ECCP2CON ) == true then + if defined( CCP2CON ) == false then + var volatile byte CCP2CON is ECCP2CON + end if +end if + +if defined( ECCP3CON ) == true then + if defined( CCP3CON ) == false then + var volatile byte CCP3CON is ECCP3CON + end if +end if + +if defined( ECCP4CON ) == true then + if defined( CCP4CON ) == false then + var volatile byte CCP4CON is ECCP4CON + end if +end if + +if defined( ECCP5CON ) == true then + if defined( CCP5CON ) == false then + var volatile byte CCP5CON is ECCP5CON + end if +end if if(defined(CCP1CON) == true) then ======================================= --- /trunk/project/pic18f14k50_usb_io/examples/usb_i2c_master.jal Tue Jul 28 16:31:21 2009 +++ /trunk/project/pic18f14k50_usb_io/examples/usb_i2c_master.jal Fri Jul 31 13:18:04 2009 @@ -21,6 +21,9 @@ include board_18f14k50_usb_af + +-- const bit USB_SERIAL_DEBUG = false + include delay include usb_serial include print ======================================= --- /trunk/sample/18f14k50_usb_bootloader.jal Mon Jul 27 14:40:40 2009 +++ /trunk/sample/18f14k50_usb_bootloader.jal Fri Jul 31 13:18:04 2009 @@ -86,6 +86,7 @@ var volatile bit bootloader_program_pin is pin_c4 var volatile bit bootloader_program_pin_direction is pin_c4_direction + const byte READ_VERSION = 0x00 const byte READ_FLASH = 0x01 const byte WRITE_FLASH = 0x02 ======================================= --- /trunk/sample/18f2450_pwm_led.jal Mon Jul 27 14:40:40 2009 +++ /trunk/sample/18f2450_pwm_led.jal Fri Jul 31 13:18:04 2009 @@ -60,6 +60,7 @@ pragma target EBTRB DISABLED -- boot block not protected ;@jallib section ccp +-- no specific settins yet, section required though to generate samples enable_digital_io() ======================================= --- /trunk/sample/18f2450_pwm_led_highres.jal Mon Jul 27 14:40:40 2009 +++ /trunk/sample/18f2450_pwm_led_highres.jal Fri Jul 31 13:18:04 2009 @@ -59,6 +59,7 @@ pragma target EBTRB DISABLED -- boot block not protected ;@jallib section ccp +-- no specific settins yet, section required though to generate samples enable_digital_io() ======================================= --- /trunk/sample/18f2450_pwm_sound.jal Mon Jul 27 14:40:40 2009 +++ /trunk/sample/18f2450_pwm_sound.jal Fri Jul 31 13:18:04 2009 @@ -62,6 +62,7 @@ pragma target EBTRB DISABLED -- boot block not protected ;@jallib section ccp +-- no specific settins yet, section required though to generate samples enable_digital_io() ======================================= --- /trunk/sample/18f2450_usb_bootloader.jal Mon Jul 27 14:40:40 2009 +++ /trunk/sample/18f2450_usb_bootloader.jal Fri Jul 31 13:18:04 2009 @@ -81,6 +81,7 @@ var volatile bit bootloader_program_pin is pin_b5 var volatile bit bootloader_program_pin_direction is pin_b5_direction + const byte READ_VERSION = 0x00 const byte READ_FLASH = 0x01 const byte WRITE_FLASH = 0x02 ======================================= --- /trunk/test/board/board_18f14k50_af.jal Mon Jul 27 14:40:40 2009 +++ /trunk/test/board/board_18f14k50_af.jal Fri Jul 31 13:18:04 2009 @@ -101,3 +101,7 @@ ;@jallib section bootloader var volatile bit bootloader_program_pin is pin_c4 var volatile bit bootloader_program_pin_direction is pin_c4_direction + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + ======================================= --- /trunk/test/board/board_18f2450_af.jal Sun Jul 5 01:42:39 2009 +++ /trunk/test/board/board_18f2450_af.jal Fri Jul 31 13:18:04 2009 @@ -121,3 +121,7 @@ ;@jallib section bootloader var volatile bit bootloader_program_pin is pin_b5 var volatile bit bootloader_program_pin_direction is pin_b5_direction + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + ======================================= --- /trunk/test/board/board_18f4550_af.jal Sun Jun 28 12:27:25 2009 +++ /trunk/test/board/board_18f4550_af.jal Fri Jul 31 13:18:04 2009 @@ -170,3 +170,7 @@ ;@jallib section bootloader var volatile bit bootloader_program_pin is pin_b5 var volatile bit bootloader_program_pin_direction is pin_b5_direction + +;@jallib section ccp +-- no specific settins yet, section required though to generate samples + --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "jallib" group. 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