Revision: 1213
Author: jsuijs
Date: Mon Aug 17 01:57:29 2009
Log: Finalized jseven - samples added, changelog & torelease updated.
http://code.google.com/p/jallib/source/detail?r=1213

Added:
  /trunk/sample/16f877a_jseven.jal
  /trunk/sample/18f4550_jseven.jal
Modified:
  /trunk/CHANGELOG
  /trunk/TORELEASE
  /trunk/include/external/seven/jseven.jal
  /trunk/test/board/board_16f877a_dwarf.jal
  /trunk/test/board/board_18f4550_af.jal

=======================================
--- /dev/null
+++ /trunk/sample/16f877a_jseven.jal    Mon Aug 17 01:57:29 2009
@@ -0,0 +1,70 @@
+-- ------------------------------------------------------
+-- Title: Test program for jseven (seven segment display
+--
+-- Author: Joep Suijs, Copyright (c) 2009..2009, all rights reserved.
+--
+-- Adapted-by:
+--
+-- Compiler: >=2.4g
+--
+-- This file is part of jallib (http://jallib.googlecode.com)
+-- Released under the BSD license  
(http://www.opensource.org/licenses/bsd-license.php)
+--
+-- Description: Testing lcd_backlight
+-- --
+-- This file defines a test for JALLIB testing, using a test-board
+--  defined by a BOARD file .
+--
+-- Sources:
+--
+-- Notes:
+-- setup:   A seven segment display connected to a port
+--
+-- ------------------------------------------------------
+--
+-- This file has been generated from:
+--    * board: board_16f877a_dwarf.jal
+--    * test : test_jseven.jal
+--
+
+;@jallib section chipdef
+-- chip setup
+include 16f877a
+
+pragma target clock 20_000_000                  -- xtal frequency
+pragma target OSC        hs
+pragma target   LVP disabled
+pragma target   WDT disabled
+
+enable_digital_io() -- disable analog I/O (if any)
+
+include delay
+;@jallib section jseven
+-- constant for the segments      gfe dcba
+const byte seven_segment_a  = 0b_0000_0001
+const byte seven_segment_b  = 0b_0000_0010
+const byte seven_segment_c  = 0b_0000_0100
+const byte seven_segment_d  = 0b_0000_1000
+const byte seven_segment_e  = 0b_0001_0000
+const byte seven_segment_f  = 0b_0010_0000
+const byte seven_segment_g  = 0b_0100_0000
+const byte seven_segment_dp = 0b_1000_0000
+include jseven
+
+portd_direction = all_output
+
+
+var byte i = 0
+forever loop
+
+   -- set backlight off for two seconds
+   portd = seven_from_digit(i) -- display char
+   delay_1ms(500)
+
+   i = i + 1
+   if (i > 17) then
+      i = 0
+   end if
+
+
+end loop
=======================================
--- /dev/null
+++ /trunk/sample/18f4550_jseven.jal    Mon Aug 17 01:57:29 2009
@@ -0,0 +1,104 @@
+-- ------------------------------------------------------
+-- Title: Test program for jseven (seven segment display
+--
+-- Author: Joep Suijs, Copyright (c) 2009..2009, all rights reserved.
+--
+-- Adapted-by:
+--
+-- Compiler: >=2.4g
+--
+-- This file is part of jallib (http://jallib.googlecode.com)
+-- Released under the BSD license  
(http://www.opensource.org/licenses/bsd-license.php)
+--
+-- Description: Testing lcd_backlight
+-- --
+-- This file defines a test for JALLIB testing, using a test-board
+--  defined by a BOARD file .
+--
+-- Sources:
+--
+-- Notes:
+-- setup:   A seven segment display connected to a port
+--
+-- ------------------------------------------------------
+--
+-- This file has been generated from:
+--    * board: board_18f4550_af.jal
+--    * test : test_jseven.jal
+--
+
+;@jallib section chipdef
+-- chip setup
+include 18f4550
+
+-- even though the external crystal is 20 MHz, the configuration is such  
that
+-- the CPU clock is derived from the 96 Mhz PLL clock (div2), therefore set
+-- target frequency to 48 MHz
+pragma target clock       48_000_000
+
+
+-- fuses
+pragma target PLLDIV           DIVIDE_BY_5__20MHZ_INPUT_
+pragma target CPUDIV           _OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_
+pragma target USBPLL           CLOCK_SRC_FROM_96MHZ_PLL_2
+pragma target OSC                      HS_PLL
+pragma target FCMEN                    DISABLED
+pragma target IESO                     DISABLED
+pragma target PWRTE                    DISABLED        -- power up timer
+pragma target VREGEN           ENABLED         -- USB voltage regulator
+pragma target VOLTAGE          V20                     -- brown out voltage
+pragma target BROWNOUT         DISABLED        -- no brownout detection
+pragma target WDTPS                    P32768          -- watch dog saler 
setting
+pragma target WDT                      DISABLED    -- no watchdog
+pragma target CCP2MUX          RC1                     -- CCP2 pin
+pragma target PBADEN           DIGITAL         -- digital input port<0..4>
+pragma target LPT1OSC          DISABLED        -- low power timer 1
+pragma target MCLR                     EXTERNAL        -- master reset on RE3
+pragma target STVR                     DISABLED    -- reset on stack 
over/under flow
+pragma target LVP                      DISABLED    -- no low-voltage 
programming
+pragma target XINST                    ENABLED         -- extended instruction 
set
+pragma target BACKBUG          DISABLED        -- background debugging
+pragma target CP_0                     DISABLED        -- code block 0 not 
protected
+pragma target CP_1                     DISABLED        -- code block 1 not 
protected
+pragma target CP_2                     DISABLED        -- code block 2 not 
protected
+pragma target CP_3                     DISABLED        -- code block 3 not 
protected
+pragma target CPB                      DISABLED        -- bootblock code not 
write protected
+pragma target CPD                      DISABLED        -- eeprom code not 
write protected
+pragma target WRT_0                    DISABLED        -- table writeblock 0 
not protected
+pragma target WRT_1                    DISABLED        -- table write block 1 
not protected
+pragma target WRT_2                    DISABLED        -- table write block 2 
not protected
+pragma target WRT_3                    DISABLED        -- table write block 3 
not protected
+pragma target WRTB                     DISABLED        -- bootblock not write 
protected
+pragma target WRTD                     DISABLED        -- eeprom not write 
protected
+pragma target WRTC                     DISABLED        -- config not write 
protected
+pragma target EBTR_0           DISABLED        -- table read block 0 not 
protected
+pragma target EBTR_1           DISABLED        -- table read block 1 not 
protected
+pragma target EBTR_2           DISABLED        -- table read block 2 not 
protected
+pragma target EBTR_3           DISABLED        -- table read block 3 not 
protected
+pragma target EBTRB            DISABLED        -- boot block not protected
+
+
+enable_digital_io() -- disable analog I/O (if any)
+
+include delay
+;@jallib section jseven
+-- use default setup from jseven.jal
+include jseven
+
+portd_direction = all_output
+
+
+var byte i = 0
+forever loop
+
+   -- set backlight off for two seconds
+   portd = seven_from_digit(i) -- display char
+   delay_1ms(500)
+
+   i = i + 1
+   if (i > 17) then
+      i = 0
+   end if
+
+
+end loop
=======================================
--- /trunk/CHANGELOG    Sun Aug 16 03:08:58 2009
+++ /trunk/CHANGELOG    Mon Aug 17 01:57:29 2009
@@ -9,7 +9,7 @@
   -

  externals:
- -
+ - jseven - library to drive an seven-segment led display.

  peripherals:
   -
@@ -18,7 +18,7 @@
   -

  samples:
- -
+ - jseven samples.

  compiler:
   -
=======================================
--- /trunk/TORELEASE    Thu Aug 13 03:19:57 2009
+++ /trunk/TORELEASE    Mon Aug 17 01:57:29 2009
@@ -149,6 +149,7 @@
  # Externals
  include/external/co2/co2_t6603.jal
  include/external/humidity/humidity_sht.jal
+include/external/jseven/jseven.jal
  include/external/keyboard/keyboard.jal
  include/external/lcd/lcd_backlight.jal
  include/external/lcd/lcd_hd44780_4.jal
@@ -336,6 +337,7 @@
  sample/16f877a_i2c_sw_l1.jal
  sample/16f877a_i2c_sw_master_check_bus.jal
  sample/16f877a_i2c_sw_master_echo.jal
+sample/16f877a_jseven.jal
  sample/16f877a_keyboard_lcd.jal
  sample/16f877a_lcd_format.jal
  sample/16f877a_lcd_hd44780_4_1.jal
@@ -493,7 +495,8 @@
  sample/18f4550_i2c_hw_slave_msg.jal
  sample/18f4550_i2c_sw_l1.jal
  sample/18f4550_i2c_sw_master_check_bus.jal
-sample/18f4550_i2c_sw_master_echo.jal
+sample/18f4550_i2c_sw_master_echo.jal
+sample/18f4550_jseven.jal
  sample/18f4550_lcd_hd44780_4.jal
  sample/18f4550_pwm_led.jal
  sample/18f4550_pwm_led_highres.jal
=======================================
--- /trunk/include/external/seven/jseven.jal    Sun Aug 16 10:54:17 2009
+++ /trunk/include/external/seven/jseven.jal    Mon Aug 17 01:57:29 2009
@@ -31,6 +31,20 @@
  -- Notes:
  --

+
+if (defined(seven_segment_a) == false) then
+   -- Default segment setup          gfe dcba
+   const byte seven_segment_a  = 0b_0000_0001
+   const byte seven_segment_b  = 0b_0000_0010
+   const byte seven_segment_c  = 0b_0000_0100
+   const byte seven_segment_d  = 0b_0000_1000
+   const byte seven_segment_e  = 0b_0001_0000
+   const byte seven_segment_f  = 0b_0010_0000
+   const byte seven_segment_g  = 0b_0100_0000
+   const byte seven_segment_dp = 0b_1000_0000
+
+end if
+
  const byte seven_value_space[] = {
     -- const byte seven_value_0
       seven_segment_a
=======================================
--- /trunk/test/board/board_16f877a_dwarf.jal   Mon Aug 17 01:35:57 2009
+++ /trunk/test/board/board_16f877a_dwarf.jal   Mon Aug 17 01:57:29 2009
@@ -98,3 +98,4 @@
  const byte seven_segment_f  = 0b_0010_0000
  const byte seven_segment_g  = 0b_0100_0000
  const byte seven_segment_dp = 0b_1000_0000
+
=======================================
--- /trunk/test/board/board_18f4550_af.jal      Sun Aug 16 12:22:14 2009
+++ /trunk/test/board/board_18f4550_af.jal      Mon Aug 17 01:57:29 2009
@@ -174,3 +174,6 @@
  ;@jallib section ccp
  -- no specific settins yet, section required though to generate samples

+;@jallib section jseven
+-- use default setup from jseven.jal
+

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