Revision: 1429 Author: robhamerling Date: Thu Oct 29 09:35:27 2009 Log: Board files updated for changes in device files revision 1427
http://code.google.com/p/jallib/source/detail?r=1429 Modified: /trunk/test/board/board_16f723_af.jal /trunk/test/board/board_16f88_js.jal /trunk/test/board/board_18f14k50_af.jal /trunk/test/board/board_18f2450_af.jal /trunk/test/board/board_18f4550_af.jal ======================================= --- /trunk/test/board/board_16f723_af.jal Wed Oct 14 11:49:00 2009 +++ /trunk/test/board/board_16f723_af.jal Thu Oct 29 09:35:27 2009 @@ -46,7 +46,7 @@ pragma target BROWNOUT DISABLED pragma target VOLTAGE V19 pragma target WDTCS STANDARD_WATCHDOG_TIMER_IS_SELECTED -pragma target PLLEN _16MHZ +pragma target PLLEN 16MHZ pragma target DEBUG DISABLED pragma target VCAPEN pin_A0 ======================================= --- /trunk/test/board/board_16f88_js.jal Sun Aug 16 16:42:16 2009 +++ /trunk/test/board/board_16f88_js.jal Thu Oct 29 09:35:27 2009 @@ -43,14 +43,14 @@ -- chip setup include 16f88 -;-- +;-- ;-- This setup assumes a 20 MHz resonator or crystal ;-- is connected to pins OSC1 and OSC2. pragma target OSC HS -- HS crystal or resonator pragma target clock 20_000_000 -- oscillator frequency pragma target WDT disabled -- no watchdog pragma target LVP disabled -- no low-voltage programming -pragma target CCP1MUX RB3 -- ccp1 pin on B3 +pragma target CCP1MUX pin_B3 -- ccp1 pin on B3 -- -- This setup uses the internal oscillator @@ -58,7 +58,7 @@ ;pragma target clock 8_000_000 -- oscillator frequency ;pragma target WDT disabled -- no watchdog ;pragma target LVP disabled -- no low-voltage programming -;pragma target CCP1MUX RB3 -- ccp1 pin on B3 +;pragma target CCP1MUX pin_B3 -- ccp1 pin on B3 ;OSCCON_IRCF = 7 -- set prescaler to 1 (8 MHz) ======================================= --- /trunk/test/board/board_18f14k50_af.jal Mon Sep 28 13:46:11 2009 +++ /trunk/test/board/board_18f14k50_af.jal Thu Oct 29 09:35:27 2009 @@ -50,32 +50,32 @@ pragma target clock 48_000_000 -- fuses -pragma target CPUDIV NO_CPU_SYSTEM_CLOCK_DIVIDE -pragma target USBDIV USB_CLOCK_COMES_DIRECTLY_FROM_THE_OSC1_OSC2_OSCILLATOR_BLOCK__NO_DIVIDE -pragma target OSC HS -pragma target PLLEN OSCILLATOR_MULTIPLIED_BY_4 -pragma target FCMEN DISABLED -pragma target IESO DISABLED -pragma target PWRTE DISABLED -- power up timer -pragma target BROWNOUT DISABLED -- no brownout detection -pragma target VOLTAGE V30 -- brown out voltage -pragma target WDT DISABLED -- no watchdog -pragma target WDTPS P32768 -- watch dog saler setting -pragma target MCLR EXTERNAL -- external reset -pragma target LVP DISABLED -- no low-voltage programming -pragma target XINST ENABLED -- extended instruction set -pragma target BACKBUG DISABLED -- background debugging -pragma target CP_0 DISABLED -- code block 0 not protected -pragma target CP_1 DISABLED -- code block 1 not protected -pragma target CPB DISABLED -- bootblock code not write protected -pragma target WRT_0 DISABLED -- table writeblock 0 not protected -pragma target WRT_1 DISABLED -- table write block 1 not protected -pragma target WRTB DISABLED -- bootblock not write protected -pragma target WRTC DISABLED -- config not write protected -pragma target EBTR_0 DISABLED -- table read block 0 not protected -pragma target EBTR_1 DISABLED -- table read block 1 not protected -pragma target EBTRB DISABLED -- boot block not protected -pragma target HFOFST THE_SYSTEM_CLOCK_IS_HELD_OFF_UNTIL_THE_HFINTOSC_IS_STABLE +pragma target CPUDIV NO_CPU_SYSTEM_CLOCK_DIVIDE +pragma target USBDIV USB_CLOCK_COMES_DIRECTLY_FROM_THE_OSC1_OSC2_OSCILLATOR_BLOCK_NO_DIVIDE +pragma target OSC HS +pragma target PLLEN OSCILLATOR_MULTIPLIED_BY_4 +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target VOLTAGE V30 -- brown out voltage +pragma target WDT DISABLED -- no watchdog +pragma target WDTPS P32768 -- watch dog saler setting +pragma target MCLR EXTERNAL -- external reset +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTRB DISABLED -- boot block not protected +pragma target HFOFST THE_SYSTEM_CLOCK_IS_HELD_OFF_UNTIL_THE_HFINTOSC_IS_STABLE ;@jallib section led @@ -98,8 +98,8 @@ ;@jallib section bootloader -alias bootloader_program_pin is pin_c4 -alias bootloader_program_pin_direction is pin_c4_direction +alias bootloader_program_pin is pin_c4 +alias bootloader_program_pin_direction is pin_c4_direction ;@jallib section ccp -- no specific settins yet, section required though to generate samples ======================================= --- /trunk/test/board/board_18f2450_af.jal Sun Aug 16 12:22:14 2009 +++ /trunk/test/board/board_18f2450_af.jal Thu Oct 29 09:35:27 2009 @@ -14,19 +14,19 @@ -- -- -- This file is the setup for my homebrew, PICDEM like 18f2450 board -- The board consist of a reset button switch to gnd (tied to pin1, with 4k7 pull up) --- A program button switch to gnd (tided to pin24, with 4k7 pull up) +-- A program button switch to gnd (tided to pin24, with 4k7 pull up) -- A 20 MHz external crystal and 15pf caps connected to OSC1/2 -- pin 14 (Vusb) with a 220 nF capacitor to the ground -- The connection between PC and the 18F2450 --- +5v to power the board +-- +5v to power the board -- data- wire to pin 15 (D-) -- data+ wire to pin 16 (D+) -- ground wire to the Vss of the PIC -- --- In addition, a MAX232 chip connccted to the USART pins, for serial (mainly to debug) +-- In addition, a MAX232 chip connccted to the USART pins, for serial (mainly to debug) -- communication. -- The board is loaded with the standard microchip bootloader, therefore the examples --- are compiled with the following JAL compiler flags: -loader18 -no-fuse +-- are compiled with the following JAL compiler flags: -loader18 -no-fuse -- -- Sources: -- Sources: http://www.microchip.org for PICDEM docs @@ -49,36 +49,36 @@ -- fuses -pragma target PLLDIV DIVIDE_BY_5__20MHZ_INPUT_ -pragma target CPUDIV _OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_ -pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 -pragma target OSC HS_PLL -pragma target FCMEN DISABLED -pragma target IESO DISABLED -pragma target PWRTE DISABLED -- power up timer -pragma target VREGEN ENABLED -- USB voltage regulator -pragma target VOLTAGE V20 -- brown out voltage -pragma target BROWNOUT DISABLED -- no brownout detection -pragma target WDTPS P32768 -- watch dog saler setting -pragma target WDT DISABLED -- no watchdog -pragma target PBADEN DIGITAL -- digital input port<0..4> -pragma target LPT1OSC DISABLED -- low power timer 1 --- pragma target MCLR EXTERNAL -- master reset on RE3 -pragma target MCLR INTERNAL -- no master reset -pragma target STVR DISABLED -- reset on stack over/under flow -pragma target LVP DISABLED -- no low-voltage programming -pragma target XINST ENABLED -- extended instruction set -pragma target BACKBUG DISABLED -- background debugging -pragma target CP_0 DISABLED -- code block 0 not protected -pragma target CP_1 DISABLED -- code block 1 not protected -pragma target CPB DISABLED -- bootblock code not write protected -pragma target WRT_0 DISABLED -- table writeblock 0 not protected -pragma target WRT_1 DISABLED -- table write block 1 not protected -pragma target WRTB DISABLED -- bootblock not write protected -pragma target WRTC DISABLED -- config not write protected -pragma target EBTR_0 DISABLED -- table read block 0 not protected -pragma target EBTR_1 DISABLED -- table read block 1 not protected -pragma target EBTRB DISABLED -- boot block not protected +pragma target PLLDIV DIVIDE_BY_5_20MHZ_INPUT_ +pragma target CPUDIV OSC1_OSC2_SRC_1_96MHZ_PLL_SRC_2 +pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 +pragma target OSC HS_PLL +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target VREGEN ENABLED -- USB voltage regulator +pragma target VOLTAGE V20 -- brown out voltage +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target WDTPS P32768 -- watch dog saler setting +pragma target WDT DISABLED -- no watchdog +pragma target PBADEN DIGITAL -- digital input port<0..4> +pragma target LPT1OSC DISABLED -- low power timer 1 +-- pragma target MCLR EXTERNAL -- master reset on RE3 +pragma target MCLR INTERNAL -- no master reset +pragma target STVR DISABLED -- reset on stack over/under flow +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTRB DISABLED -- boot block not protected ;@jallib section led @@ -114,8 +114,8 @@ ;@jallib section ccp ;@jallib section bootloader -alias bootloader_program_pin is pin_b5 -alias bootloader_program_pin_direction is pin_b5_direction +alias bootloader_program_pin is pin_b5 +alias bootloader_program_pin_direction is pin_b5_direction ;@jallib section ccp -- no specific settins yet, section required though to generate samples ======================================= --- /trunk/test/board/board_18f4550_af.jal Mon Aug 17 01:57:29 2009 +++ /trunk/test/board/board_18f4550_af.jal Thu Oct 29 09:35:27 2009 @@ -14,19 +14,19 @@ -- -- -- This file is the setup for my homebrew, PICDEM like 18f4550 board -- The board consist of a reset button switch to gnd (tided to pin1, with 4k7 pull up) --- A program button switch to gnd (tided to pin37, with 4k7 pull up) +-- A program button switch to gnd (tided to pin37, with 4k7 pull up) -- A 20 MHz external crystal and 15pf caps connected to OSC1/2 -- pin 18 (Vusb) with a 220 nF capacitor to the ground -- The connection between PC and the 18F4450 --- +5v to power the board +-- +5v to power the board -- data- wire to pin 23 (D-) -- data+ wire to pin 24 (D+) -- ground wire to the Vss of the PIC -- --- In addition, a MAX232 chip connccted to the USART pins, for serial (mainly to debug) +-- In addition, a MAX232 chip connccted to the USART pins, for serial (mainly to debug) -- communication. -- The board is loaded with the standard microchip bootloader, therefore the examples --- are compiled with the following JAL compiler flags: -loader18 -no-fuse +-- are compiled with the following JAL compiler flags: -loader18 -no-fuse -- -- Sources: -- Sources: http://www.microchip.org for PICDEM docs @@ -49,44 +49,44 @@ -- fuses -pragma target PLLDIV DIVIDE_BY_5__20MHZ_INPUT_ -pragma target CPUDIV _OSC1_OSC2_SRC___1__96MHZ_PLL_SRC___2_ -pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 -pragma target OSC HS_PLL -pragma target FCMEN DISABLED -pragma target IESO DISABLED -pragma target PWRTE DISABLED -- power up timer -pragma target VREGEN ENABLED -- USB voltage regulator -pragma target VOLTAGE V20 -- brown out voltage -pragma target BROWNOUT DISABLED -- no brownout detection -pragma target WDTPS P32768 -- watch dog saler setting -pragma target WDT DISABLED -- no watchdog -pragma target CCP2MUX RC1 -- CCP2 pin -pragma target PBADEN DIGITAL -- digital input port<0..4> -pragma target LPT1OSC DISABLED -- low power timer 1 -pragma target MCLR EXTERNAL -- master reset on RE3 -pragma target STVR DISABLED -- reset on stack over/under flow -pragma target LVP DISABLED -- no low-voltage programming -pragma target XINST ENABLED -- extended instruction set -pragma target BACKBUG DISABLED -- background debugging -pragma target CP_0 DISABLED -- code block 0 not protected -pragma target CP_1 DISABLED -- code block 1 not protected -pragma target CP_2 DISABLED -- code block 2 not protected -pragma target CP_3 DISABLED -- code block 3 not protected -pragma target CPB DISABLED -- bootblock code not write protected -pragma target CPD DISABLED -- eeprom code not write protected -pragma target WRT_0 DISABLED -- table writeblock 0 not protected -pragma target WRT_1 DISABLED -- table write block 1 not protected -pragma target WRT_2 DISABLED -- table write block 2 not protected -pragma target WRT_3 DISABLED -- table write block 3 not protected -pragma target WRTB DISABLED -- bootblock not write protected -pragma target WRTD DISABLED -- eeprom not write protected -pragma target WRTC DISABLED -- config not write protected -pragma target EBTR_0 DISABLED -- table read block 0 not protected -pragma target EBTR_1 DISABLED -- table read block 1 not protected -pragma target EBTR_2 DISABLED -- table read block 2 not protected -pragma target EBTR_3 DISABLED -- table read block 3 not protected -pragma target EBTRB DISABLED -- boot block not protected +pragma target PLLDIV DIVIDE_BY_5_20MHZ_INPUT_ +pragma target CPUDIV OSC1_OSC2_SRC_1_96MHZ_PLL_SRC_2 +pragma target USBPLL CLOCK_SRC_FROM_96MHZ_PLL_2 +pragma target OSC HS_PLL +pragma target FCMEN DISABLED +pragma target IESO DISABLED +pragma target PWRTE DISABLED -- power up timer +pragma target VREGEN ENABLED -- USB voltage regulator +pragma target VOLTAGE V20 -- brown out voltage +pragma target BROWNOUT DISABLED -- no brownout detection +pragma target WDTPS P32768 -- watch dog saler setting +pragma target WDT DISABLED -- no watchdog +pragma target CCP2MUX pin_C1 -- CCP2 pin +pragma target PBADEN DIGITAL -- digital input port<0..4> +pragma target LPT1OSC DISABLED -- low power timer 1 +pragma target MCLR EXTERNAL -- master reset on RE3 +pragma target STVR DISABLED -- reset on stack over/under flow +pragma target LVP DISABLED -- no low-voltage programming +pragma target XINST ENABLED -- extended instruction set +pragma target BACKBUG DISABLED -- background debugging +pragma target CP_0 DISABLED -- code block 0 not protected +pragma target CP_1 DISABLED -- code block 1 not protected +pragma target CP_2 DISABLED -- code block 2 not protected +pragma target CP_3 DISABLED -- code block 3 not protected +pragma target CPB DISABLED -- bootblock code not write protected +pragma target CPD DISABLED -- eeprom code not write protected +pragma target WRT_0 DISABLED -- table writeblock 0 not protected +pragma target WRT_1 DISABLED -- table write block 1 not protected +pragma target WRT_2 DISABLED -- table write block 2 not protected +pragma target WRT_3 DISABLED -- table write block 3 not protected +pragma target WRTB DISABLED -- bootblock not write protected +pragma target WRTD DISABLED -- eeprom not write protected +pragma target WRTC DISABLED -- config not write protected +pragma target EBTR_0 DISABLED -- table read block 0 not protected +pragma target EBTR_1 DISABLED -- table read block 1 not protected +pragma target EBTR_2 DISABLED -- table read block 2 not protected +pragma target EBTR_3 DISABLED -- table read block 3 not protected +pragma target EBTRB DISABLED -- boot block not protected ;@jallib section led @@ -104,46 +104,46 @@ procedure PORTLCD'put(byte in x) is - var volatile bit x_0 at x:0 - var volatile bit x_1 at x:1 - var volatile bit x_2 at x:2 - var volatile bit x_3 at x:3 - - pin_b1 = x_0 - pin_b2 = x_1 - pin_b3 = x_2 - pin_b4 = x_3 + var volatile bit x_0 at x:0 + var volatile bit x_1 at x:1 + var volatile bit x_2 at x:2 + var volatile bit x_3 at x:3 + + pin_b1 = x_0 + pin_b2 = x_1 + pin_b3 = x_2 + pin_b4 = x_3 end procedure function PORTLCD'get() return byte is - var byte ret - var volatile bit ret_0 at ret:0 = pin_b1 - var volatile bit ret_1 at ret:1 = pin_b2 - var volatile bit ret_2 at ret:2 = pin_b3 - var volatile bit ret_3 at ret:3 = pin_b4 - return ret + var byte ret + var volatile bit ret_0 at ret:0 = pin_b1 + var volatile bit ret_1 at ret:1 = pin_b2 + var volatile bit ret_2 at ret:2 = pin_b3 + var volatile bit ret_3 at ret:3 = pin_b4 + return ret end function procedure PORTLCD_direction'put(byte in x) is - var volatile bit x_0 at x:0 - var volatile bit x_1 at x:1 - var volatile bit x_2 at x:2 - var volatile bit x_3 at x:3 - - pin_b1_direction = x_0 - pin_b2_direction = x_1 - pin_b3_direction = x_2 - pin_b4_direction = x_3 + var volatile bit x_0 at x:0 + var volatile bit x_1 at x:1 + var volatile bit x_2 at x:2 + var volatile bit x_3 at x:3 + + pin_b1_direction = x_0 + pin_b2_direction = x_1 + pin_b3_direction = x_2 + pin_b4_direction = x_3 end procedure function PORTLCD_direction'get() return byte is - var byte ret - var volatile bit ret_0 at ret:0 = pin_b1_direction - var volatile bit ret_1 at ret:1 = pin_b2_direction - var volatile bit ret_2 at ret:2 = pin_b3_direction - var volatile bit ret_3 at ret:3 = pin_b4_direction - return ret + var byte ret + var volatile bit ret_0 at ret:0 = pin_b1_direction + var volatile bit ret_1 at ret:1 = pin_b2_direction + var volatile bit ret_2 at ret:2 = pin_b3_direction + var volatile bit ret_3 at ret:3 = pin_b4_direction + return ret end function -- LCD IO definition @@ -168,8 +168,8 @@ ;@jallib section bootloader -alias bootloader_program_pin is pin_b5 -alias bootloader_program_pin_direction is pin_b5_direction +alias bootloader_program_pin is pin_b5 +alias bootloader_program_pin_direction is pin_b5_direction ;@jallib section ccp -- no specific settins yet, section required though to generate samples --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/jallib?hl=en -~----------~----~----~----~------~----~------~--~---
