On Tue, Jul 27, 2010 at 3:14 PM, Rob Hamerling <[email protected]>wrote:
> > > On 07/27/10 12:45 pm, vasile surducan wrote: > >> >> Two different procedures with the same result: >> >> A: >> -- ---------------------------------------------------------------------- >> -- Enable RTCC register writes >> -- input: bit (enable / disable) >> -- output: none >> -- returns: nothing >> -- notes: Setting the RTCWREN bit in RTCCFG requires a strict >> -- sequence, some assembly language need to be used. >> -- ---------------------------------------------------------------------- >> procedure _rtc_write_control(bit in control) is >> >> asm bank RTCCFG -- set bank of RTCCFG >> if (control == enabled) then >> EECON2 = 0x55 -- ) write .. >> EECON2 = 0xAA -- ) .. enable >> RTCCFG_RTCWREN = enabled -- allow writes >> else >> EECON2 = 0x55 -- ) write .. >> EECON2 = 0xAA -- ) .. enable >> RTCCFG_RTCWREN = disabled -- deny writes >> end if >> >> end procedure >> >> >> B: >> -- ---------------------------------------------------------------------- >> -- Enable RTCC register writes >> -- input: bit (RTC_enabled / RTC_disabled) >> -- ---------------------------------------------------------------------- >> >> const bit RTC_enabled = 1 >> const bit RTC_disabled = 0 >> procedure RTC_writing (bit in value) is >> asm bank RTCCFG ; identical with RTCCFG_RTCWREN = value used only to >> set bank 15 >> EECON2 = 0x55 -- \ required sequence >> EECON2 = 0xAA -- / >> RTCCFG_RTCWREN = value ; enable/disable writting to RTCCFG >> end procedure >> >> > Both may work, but neither expand to the Microchip datasheet prescribed > instruction sequence! Both violate the following statement in the datasheet: > > "For the RTCWREN bit to be set, there > "is only one instruction cycle time window allowed > "between the 55h/AA sequence and the setting of > "RTCWREN. > I didn't noticed this until you've pointed to... :( I guess assembler can solve the Microchip instruction sequence. But still curious if this work on PPS registers where assembler is suggested for all C lovers. Vasile > > The following code does expand to the required instruction sequence: > > > if (control == enabled) then > > asm bank RTCCFG > > EECON2 = 0x55 > > EECON2 = 0xAA > > RTCCFG_RTCWREN = enabled > > else > > asm bank RTCCFG > > EECON2 = 0x55 > > EECON2 = 0xAA > > RTCCFG_RTCWREN = disabled > > end if > > Regards, Rob. > > -- > Rob Hamerling, Vianen, NL (http://www.robh.nl/) > > > -- > You received this message because you are subscribed to the Google Groups > "jallib" group. > To post to this group, send email to [email protected]. > To unsubscribe from this group, send email to > [email protected]<jallib%[email protected]> > . > For more options, visit this group at > http://groups.google.com/group/jallib?hl=en. > > -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
