Hi guys,
This is buildbot speaking. I have finished a build of jallib-standard on jallib.
Buildslave for this Build: sebbot
Build Reason:
Build Source Stamp: HEAD
Blamelist: robhamerling
BUILD FAILED: failed validate compile
Logs are attached.
sincerely,
-The Buildbot
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U CHANGELOG
Updated to revision 2172.
749 samples to validate...
494 libraries to validate...
1 files can't be validated...
List:
rtc_isr_tmr3.jal
Details:
-- jsg output --
File:
/hdc1/home/sirloon/jallib/slave/standard/build/include/jal/rtc_isr_tmr3.jal
1 errors found
ERROR: rtc_isr_tmr3.jal:Cannot find end of field content Notes
0 warnings found
-- -- --
Environment config
JALLIB_ROOT=/hdc1/home/sirloon/jallib/slave/standard/build
JALLIB_REPOS=/hdc1/home/sirloon/jallib/slave/standard/build/include
JALLIB_SAMPLEDIR=/hdc1/home/sirloon/jallib/slave/standard/build/sample
JALLIB_JALV2=/home/sirloon/bin/jalv24n-beta
JALLIB_PYTHON=python2.5
Time duration: 617 secs
jal 2.4n-beta (compiled Feb 26 2010)
Required parameter to hex is missing!
no source file, use /home/sirloon/bin/jalv24n-beta --help for help
Error while compiling file (status=1).
See previous message.
749 samples to compile...
1 samples can't be compiled...
List:
18f26j11_rtc_hardware.jal
Details:
sample:
/hdc1/home/sirloon/jallib/slave/standard/build/sample/18f26j11_rtc_hardware.jal
... Failed
-- jalv2 output --
jal 2.4n-beta (compiled Feb 26 2010)
generating p-code
0 errors, 0 warnings
3483 tokens, 215480 chars; 4860 lines; 9 files
generating PIC code pass 1
generating PIC code pass 2
writing result
/hdc1/home/sirloon/jallib/slave/standard/build/sample/18f26j11_rtc_hardware.jal:683:
illegal instruction
Error while compiling file (status=1).
See previous message.
-- -- --
Environment config
JALLIB_ROOT=/hdc1/home/sirloon/jallib/slave/standard/build
JALLIB_REPOS=/hdc1/home/sirloon/jallib/slave/standard/build/include
JALLIB_SAMPLEDIR=/hdc1/home/sirloon/jallib/slave/standard/build/sample
JALLIB_JALV2=/home/sirloon/bin/jalv24n-beta
JALLIB_PYTHON=python2.5
Time duration: 1514 secs
