> [...] or maybe there is a way to detect if it is > supported on the > current PIC.
As far as I know, if there is a POSTINC1, there's three sets of INDF registers with all the features. But, to make use of a POSTINC register, you have to rely on the compiler not changing what you have written to the correspondent FSRxL, FSRxH registers. There's no way to find out but to check the contents of those registers, and this takes far more time than just setting the registers again before any access to a INDF register. For now it is confirmed that "the compiler does not use INDF1 or INDF2 yet." So, until this changes, it's no problem. But if this changes, trouble's ahead. > If it is not, use a normal array + counter > method. I don't really know how the compiler handles arrays. But, if the compiler starts to use more than one INDF, array handling will probably speed up a lot. > I'll have to test file read/write times on hard disk & > sd card. If > there is a big difference, it would be worth it. If it is for copying sequential memory locations to other sequential memory locations, performance could rise a real lot, especially when using POSTINC1 *and* POSTINC2. One byte could then be copied in only 5 instruction cycles, while when only using one INDF, I think about 20 cycles are needed. Greets, Kiste -- You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/jallib?hl=en.
