Hi Matt, As you might have noticed I'm cleaning up the sample directory so it takes less effort to maintain. So could you please:
1. add a line like -- This file has been generated by <your_methode> to each sample you've generated? 2. only generate sampels with a 'namespace' (filename without the device part) that is exclusively used by your methode? Thanks, Joep 2014-03-04 5:09 GMT+01:00 mattschinkel <[email protected]>: > Hi guys, > > I had a chance to test this sample. The sample stops output half way > through the program. I found that it works after changing the device part > of the sample. I'm not sure if it is due to compiler version or new device > files. > > Other 18f67j50 samples may have issues. I will re-generate them. I don't > know much about most of the parameters, so if anyone spots the issue, let's > see if there are issues with other samples. > > The current code that does not work is: > > include 18f67j50 -- target PICmicro > -- include chip > pragma target clock 48_000_000 -- oscillator frequency > -- configuration memory settings (fuses) > pragma target WDT CONTROL -- no watchdog > pragma target PLLDIV P2 -- divide by 2 > pragma target CPUDIV P1 -- no cpu system clock divide > pragma target OSC INTOSC_NOCLKOUT_PLL -- internal resonator > pragma target IESO DISABLED > pragma target FCMEN DISABLED > OSCTUNE_PLLEN = 1 -- set 96mhz pll > OSCCON_SCS = 0b00 > _usec_delay(1_000) -- wait for OSC PLL to settle > -- > enable_digital_io() -- disable all analog pins if any > > > > When I change it to match Robs 18f67j50_blink_usb, it works. > > include 18f67j50 -- target PICmicro > -- > -- Compiler directives > pragma target CLOCK 48_000_000 -- CPU frequency > -- > -- Configuration memory settings (fuses) > pragma target OSC INTOSC_NOCLKOUT_PLL -- HS crystal or resonator > -- and using PLL > pragma target PLLDIV P2 -- reduce OSC 20->4 MHz for PLL input > pragma target CPUDIV P1 -- CPU freq. from PLL(96/2): 48 MHz > pragma target FCMEN DISABLED -- no fail-safe clock monitoring > pragma target IESO DISABLED -- no in/ext oscillator switchover > pragma target WDT CONTROL -- no watchdog > pragma target XINST DISABLED -- not supported by JalV2 > pragma target DEBUG DISABLED -- no debugging > -- > -- Note: Not specified: > -- Code protection, Boot Block Code protection, Data EEPROM > protection, > -- Write protection, Configuration Memory write protection, > -- Table Read protection, Boot Block Table Read protection, > -- and maybe some other configuration bits. > -- > OSCCON_SCS = 0b00 -- select primary clock source > OSCTUNE_PLLEN = enabled -- activate PLL module > -- > WDTCON_SWDTEN = OFF -- disable WDT > -- > enable_digital_io() -- make all pins digital I/O > > -- > You received this message because you are subscribed to the Google Groups > "jallib" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > To post to this group, send email to [email protected]. > Visit this group at http://groups.google.com/group/jallib. > For more options, visit https://groups.google.com/groups/opt_out. > -- You received this message because you are subscribed to the Google Groups "jallib" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/jallib. For more options, visit https://groups.google.com/groups/opt_out.
