Hi Kiste,

Thanks for the info. Must have been some work to find that out 🙂.

I made changes to the Python script that generate the device files and I added 
a new pragma for the compiler.

In onder to determine for which PIC I need to change the instruction set I used 
the instruction set information provided by Microchip. The other Rob has sent 
me a list of all PICs and which instruction set they use and based on that I 
could also confirm that this is the way forward.

I am running some tests and it seems that it works OK. If I have sufficient 
time I will finish it this weekend and maybe be on time to upload it all for 
the next bee package.

As said I will also update all device files with the new pragma and a new build 
of the compiler since only the new built compiler can handle it.

Kind regards,

Rob

________________________________
Van: 'Oliver Seitz' via jallib <[email protected]>
Verzonden: dinsdag 17 november 2020 16:40
Aan: [email protected] <[email protected]>
Onderwerp: Re: [jallib] RAM not working on larger chip

Hi!

I'm checkin on another base of data. I've downloaded 244 datasheets, 66 of 
which contain more than 1* occurrence of "LFSR". All of those explain one of 
two possible bitfield patterns, which are the patterns for 12 and 14 bit we 
discussed.

Manually reading the results, I can confirm that only these families do have 14 
bit:

*k42
*k83
*q40
*q41
*q43
*q84

That is, if I did catch all of the relevant data sheets.

Greets,
Kiste


* 1 occurrence is used as abbreviation for "Linear Feedback Shift Register"




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