The previous interfaces from registers_64.c were no longer valid and had
to be updated according to x86-32 code.
Signed-off-by: Eduard - Gabriel Munteanu <eduard.munte...@linux360.ro>
---
arch/x86/include/arch/registers_64.h | 3 ++
arch/x86/registers_64.c | 53 +++++++++++++++++++++-------------
2 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/arch/registers_64.h
b/arch/x86/include/arch/registers_64.h
index d3330e3..5efa48a 100644
--- a/arch/x86/include/arch/registers_64.h
+++ b/arch/x86/include/arch/registers_64.h
@@ -4,6 +4,8 @@
#include <limits.h>
#include <stdbool.h>
+#include "vm/types.h"
+
enum machine_reg {
MACH_REG_RAX, /* R0 */
MACH_REG_RCX, /* R1 */
@@ -46,6 +48,7 @@ enum machine_reg {
const char *reg_name(enum machine_reg reg);
enum machine_reg_type reg_type(enum machine_reg reg);
+bool reg_supports_type(enum machine_reg reg, enum vm_type type);
static inline bool is_caller_saved_reg(enum machine_reg reg)
{
diff --git a/arch/x86/registers_64.c b/arch/x86/registers_64.c
index af0a219..641c3f8 100644
--- a/arch/x86/registers_64.c
+++ b/arch/x86/registers_64.c
@@ -29,23 +29,6 @@
#include <assert.h>
-static enum machine_reg_type register_types[] = {
- [MACH_REG_RAX] = REG_TYPE_GPR,
- [MACH_REG_RBX] = REG_TYPE_GPR,
- [MACH_REG_RCX] = REG_TYPE_GPR,
- [MACH_REG_RDX] = REG_TYPE_GPR,
- [MACH_REG_RDI] = REG_TYPE_GPR,
- [MACH_REG_RSI] = REG_TYPE_GPR,
- [MACH_REG_R8] = REG_TYPE_GPR,
- [MACH_REG_R9] = REG_TYPE_GPR,
- [MACH_REG_R10] = REG_TYPE_GPR,
- [MACH_REG_R11] = REG_TYPE_GPR,
- [MACH_REG_R12] = REG_TYPE_GPR,
- [MACH_REG_R13] = REG_TYPE_GPR,
- [MACH_REG_R14] = REG_TYPE_GPR,
- [MACH_REG_R15] = REG_TYPE_GPR,
-};
-
static const char *register_names[] = {
[MACH_REG_RAX] = "RAX",
[MACH_REG_RCX] = "RCX",
@@ -73,9 +56,39 @@ const char *reg_name(enum machine_reg reg)
return register_names[reg];
}
-enum machine_reg_type reg_type(enum machine_reg reg)
+#define GPR_64 (1UL << J_LONG) | (1UL << J_REFERENCE)
+#define GPR_32 (1UL << J_INT)
+#define GPR_16 (1UL << J_SHORT) | (1UL << J_CHAR)
+#define GPR_8 (1UL << J_BYTE) | (1UL << J_BOOLEAN)
+#define FPU (1UL << J_FLOAT) | (1UL << J_DOUBLE)
+
+bool reg_supports_type(enum machine_reg reg, enum vm_type type)
{
- assert(reg != MACH_REG_UNASSIGNED);
+ static const uint32_t table[NR_REGISTERS] = {
+ [MACH_REG_RAX] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_RCX] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_RDX] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_RBX] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R8] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R9] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R10] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R11] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R12] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R13] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R14] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_R15] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+
+ /* XXX: We can't access the lower nibbles of these registers,
+ * so they shouldn't have GPR_16 or GPR_8, but we need it for
+ * now to work around a reg-alloc bug. */
+ [MACH_REG_RSI] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ [MACH_REG_RDI] = GPR_64 | GPR_32 | GPR_16 | GPR_8,
+ };
+
+ assert(reg < NR_REGISTERS);
+ assert(type < VM_TYPE_MAX);
+ assert(type != J_VOID);
+ assert(type != J_RETURN_ADDRESS);
- return register_types[reg];
+ return table[reg] & (1UL << type);
}
--
1.6.0.6
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