Position: Validation Engineer

Location: OR

Duration: 6 months

*3+ years using Pathmill to converge circuit designs, timing analysis, and
signal edge rates**
- signal integrity
- pathmill timing analysis
- ERCs*

Project Description: Electromagnetic QPI/PCIe probing ASIC on Intel's
45nanometer process
Daily Responsibilities: Run and analyze analog and/or digital circuit
simulations. Make the necessary modifications for circuits to meet
performance targets.
- Run layout extraction.
- Work with the mask design team to ensure layout is completed to
engineering requirements.
- Run static timing analysis for digital circuits and ensure they meet
performance targets.
- Perform Function Equivalence Verification
- Validate circuit functionality with mixed signal verification.

Necessary Skills (Must Have):
Demonstrable knowledge of transistor level circuit design and optimization
at a level that meets with our basic requirements for the position
- Use and familiarity with timing tools (Pathmill, Prime-time), Parasitic
extraction (StarRC-XT), transistor circuit simulation, mixed signal
validation (VCS(R) and/or nanosim(R), ADMS), Register Transfer Level (RTL) to
schematic verification tools (Verplex and/or Conformal), and Design Rule
Checking (DRC) and/or LVS (Hercules)
- Ability to work well in a diverse team environment
- Excellent written and verbal communications skills
- A minimum of three years of previous experience and/or exposure to the
design of IOs, PLLs, DLLs or memories design experience
Additional Skills Desired (Nice to Have): Design experience with high speed
serial IO, QPI or PCIe* would be an added advantage





Plz send resumes to [EMAIL PROTECTED]



Thanks and Regards

RAVI TEJA

903-841-5158
Y! : "ravi_gci"

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