******** PLEASE RESPOND TO [email protected] *************** ****************DIRECT CLIENT *************
********INTERVIEWS ASAP*********** * * ** *Location: Austin, TX* * Duration: 6 months * * * *2 Positions for Verification Engineers:* *ASIC / FPGA Verification using OVM or VMM*. *Extensive Hands-on* experience in System Verilog and Verilog. Verification experience in *PCIe, HDMI, HD-SDI, Image Processing Pipeline, DDR3C, H.264, XAUI, J2K Decode*r etc. logic block is preferrable. Cadence NC-Sim tool exposure is highly desirable. ** Thanks!! Vivek Samant Resource Manager Optimum Technology Solutions Inc. ********************************************* Consistently delivering optimum, cost effective, valuable IT-based solutions to our clients Optimum Technology Solutions Inc., Phone: 615-346-9325 Fax : 615-523-2880 Email: [email protected] www.optyinc.com -- You received this message because you are subscribed to the Google Groups "Java Tech Group" group. To post to this group, send email to [email protected]. To unsubscribe from this group, send email to [email protected]. For more options, visit this group at http://groups.google.com/group/java-tech-group?hl=en.
