Just in case, you are welcome to join this GSoC project as a mentor.

P.S: Vivado would be cool

BR, Oleg


суббота, 3 февраля 2018 г., 21:02:04 UTC+1 пользователь Derrick Gibelyou 
написал:
>
> Thanks,
>
> If I could go  back in time, I think I could have pulled this off as a 
> masters project.  Sigh.
>
> I am hoping that once there is something out there that is open source 
> then it will be easier for people like yourself to get approval for 
> contributing small patches.  It would be even cooler if the Tools vendors 
> decided to contribute.
>
> I think I will start with just the Xilinx Vivado Utilization based on the 
> Memory Map plugin, and then wait to see what comes out of the GSoC.  That 
> could be really exciting.
>
>
> On Thursday, February 1, 2018 at 3:45:01 AM UTC-7, Oleg Nenashev wrote:
>>
>> Hi Derrick,
>>
>> It would be great to see that in open-source.
>> I have previously implemented plugins for dozens of EDA tools at my 
>> previous jobs, but I was unable to get approvals to publish them.
>>
>>    - My approach in OSS would be to create mini-plugins for each tool 
>>    separately so they get independent release cycles.
>>    - Many existing plugins (like Warnings) have extension points so that 
>>    they can be used in external plugins. New extension points can be added 
>>    on-demand.
>>    - Improvements to existing plugins (like hierarchical utilization) 
>>    would be really useful if they are implemented in a generic way
>>    
>> FYI we also have a GSoC project idea about EDA tools: 
>> https://jenkins.io/projects/gsoc/gsoc2018-project-ideas/#integration-plugin-s-for-electronic-design-automation-tools.
>>  
>>
>>
>> Hopefully it helps,
>> Oleg
>>
>> четверг, 1 февраля 2018 г., 3:00:11 UTC+1 пользователь Derrick Gibelyou 
>> написал:
>>>
>>> Are there any plugins for FPGA development that I can contribute to?
>>>
>>> I have been using and abusing a few software centric plugins, and am 
>>> finally ready to put in some effort to get something better. I have used 
>>> the Warning plugin with custom regex to create parser for the tools we use 
>>> (Vivado, Modelsim, Quartus).  I have also abused the PMD plugin to display 
>>> long paths (too may LUTs between Flops), but that gets confusing unless you 
>>> know how I mapped 'packages' to 'source clock' and line number to number of 
>>> LUTs.  I have used the plots plugin to try to plot utilization, with 
>>> mediocre results.
>>>
>>> My plan for creating an FPGA plugin would be to take several existing 
>>> plugins and extend them to be more applicable to FPGA development.  
>>> First I would implement my custom regex in Java code by extending the 
>>> Warning Plugin.  Then I will extend the Memory Map plugin to work for 
>>> FPGA resources.  Eventually I would like to create intuitive reports 
>>> for hierarchical utilization (By extending SLOCCount?) and warn about long 
>>> paths (Maybe by extending a cyclomatic complexity plugin?)
>>>
>>> Are there any good starting points, or should I plow ahead and make my 
>>> own plugin?
>>>
>>>

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