On Fri, Oct 21, 2011 at 6:24 AM, Pavel Lunin <[email protected]> wrote: >> http://tools.ietf.org/html/draft-ietf-mpls-entropy-label-00 > > Keeping in mind what we discussed in the next thread, it's way too > complicated for the cheap ASICs, used in ethernet switches. Most of them, as > far as I understand, are just hardcoded to extract bits with given offsets > and that's all. In addition, looks like they have a limited-size memory > cells (registers or whatever), on which they can do xor/mod/cmp/etc for the > hash-key calculations and hash-key->next-hop mapping.
Size of one MPLS header: 4 octets Size of one IPv6 header (w/o TCP, etc.) 40 octets Since many of these devices have IPv6 routing capability (with a limited FIB size) it is certain that they can look far enough into the packet to see as many labels as any reasonable design will require. Whether or not they have the ability to understand those labels is another matter; but if a chip can route IPv6 it can sure see as many labels as you are likely to require. On Fri, Oct 21, 2011 at 7:21 AM, Pavel Lunin <[email protected]> wrote: > BTW, this is why I'm quite sceptically looking at the Juniper's marketing of > Express Chip simplicity and corresponded benefits. Lower number of I share your skeptical view of the PTX. The power requirements they have published (estimates, I imagine) are relatively high and FCS density is not terribly exciting. I hear the price is also not going to be very exciting. They have not said how much buffer it will have, which would contribute to energy consumption. As far as how they have decided to implement PTX, I guess if you are a big enough customer, you can just ask them. The forwarding look-up itself is trivial and, assuming packets are arriving at a rate of 300MHz (two 100GbE interfaces) you could do it without any off-die memory at all, which means you save pins and power by eliminating off-chip memory banks. The internal buffering / queuing across the system fabric is probably more complicated than the destination look-up. QoS is another complexity. i doubt it is quite as simple as "install less SRAM and rate the ALUs for more Mpps because they are doing less work per packet," but certainly one area of the process does get much less complicated. -- Jeff S Wheeler <[email protected]> Sr Network Operator / Innovative Network Concepts _______________________________________________ juniper-nsp mailing list [email protected] https://puck.nether.net/mailman/listinfo/juniper-nsp
