Interesting to see that Hyper-mode is useless on MX204, by the way (it's 
expected to do something on MPC7).

> Le 31 janv. 2019 à 16:46, [email protected] a écrit :
> 
> Hmm interesting, so it's capped at the WA block then not on the ASIC, good to 
> know.
> On MPC7s we did not run into this issue but rather to the chip overload 
> problem
> From my notes:
> MPC7 24x10GE per PFE that is 2x212.773Mpps (425.546Mpps two directions) -> 
> 17.73Mpps per 10GE
> MPC7 20x10GE per PFE that is 2x212.773Mpps (425.546Mpps two directions) -> 
> 21.28Mpps per 10GE
> Just for reference:
> Line-rate 10Gbps@L2(64B)@L1(84B) is 29.761Mpps (two directions
> 
> Under NDA you can get what juniper tested internally, some graphs etc..
> But it's better to do your own testing (in a specific use case)
> 
> See the full linerate performance is not there so that you can send 64b 
> packets at 100G no one would do that -but it's terher to give you some 
> headroom to send packets of normal size and do some processing while 
> maintaining the performance.
> So yes with 100GE capable chips you have to be careful nowadays on what 
> features you enable. 

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