PatchSet 6438
Date: 2005/05/06 15:24:20
Author: guilhem
Branch: HEAD
Tag: (none)
Log:
Symbol rename. GC fixes. Thread & Network fixlet. Test cleanup.
* kaffe/kaffevm/classMethod.c,
(resolveInterfaces): Hold a strong reference on interfaces to
prevent it from being garbage collected before the destruction of
the class object.
* kaffe/kaffevm/gcFuncs.c
(destroyClass): Remove the strong reference.
(walkClass): Do not walk interfaces anymore as there is already a
strong reference on it.
* kaffe/kaffevm/utf8const.c
(utf8ConstInit): Symbol cleanup for kaffeh.
* kaffe/kaffevm/kaffe-gc/gc-refs.c
(KaffeGC_addWeakRef): Release the lock before going into malloc and
acquire it again after.
* kaffe/kaffevm/systems/unix-pthreads/thread-impl.c:
(jthread_exit) Fixed jthread_exit in case of unexpected error
returned by repsem_wait.
* config/sysdepCallMethod-ffi.h,
config/alpha/jit-alpha.def,
config/arm/jit3-arm.def,
config/i386/jit-i386.def,
config/i386/jit3-i386.def,
config/m68k/jit-m68k.def,
config/m68k/jit3-m68k.def,
config/powerpc/jit3-powerpc.def,
config/sparc/jit-sparc.def,
kaffe/kaffevm/baseClasses.c,
kaffe/kaffevm/classMethod.c,
kaffe/kaffevm/code-analyse.c,
kaffe/kaffevm/exception.c,
kaffe/kaffevm/external.c,
kaffe/kaffevm/findInJar.c,
kaffe/kaffevm/gtypes.h,
kaffe/kaffevm/itypes.c,
kaffe/kaffevm/jar.c,
kaffe/kaffevm/kaffe.def,
kaffe/kaffevm/reference.c,
kaffe/kaffevm/stackTrace.c,
kaffe/kaffevm/support.c,
kaffe/kaffevm/thread.c,
kaffe/kaffevm/gcj/gcj-except.c,
kaffe/kaffevm/intrp/machine.c,
kaffe/kaffevm/jit/basecode.c,
kaffe/kaffevm/jit/icode.c,
kaffe/kaffevm/jit/labels.c,
kaffe/kaffevm/jit/machine.c,
kaffe/kaffevm/jit/registers.c,
kaffe/kaffevm/jit3/basecode.c,
kaffe/kaffevm/jit3/icode.c,
kaffe/kaffevm/jit3/machine.c,
kaffe/kaffevm/jit3/registers.c,
kaffe/kaffevm/kaffe-gc/gc-incremental.c,
kaffe/kaffevm/kaffe-gc/gc-mem.c,
kaffe/kaffevm/systems/beos-native/signal.c,
kaffe/kaffevm/systems/oskit-pthreads/signal.c,
kaffe/kaffevm/systems/unix-pthreads/thread-impl.c,
libraries/clib/native/Method.c,
libraries/clib/native/Runtime.c: Renamed ABORT and EXIT to
KAFFEVM_ABORT and KAFFEVM_EXIT.
* libraries/javalib/gnu/java/net/PlainSocketImpl.java:
(connect) Imported internal checkings for socketConnect from GNU
Classpath.
* test/regression/SerialUID.java: Report the full stack trace of
the exception.
Members:
ChangeLog:1.3966->1.3967
config/sysdepCallMethod-ffi.h:1.1->1.2
config/alpha/jit-alpha.def:INITIAL->1.14
config/arm/jit3-arm.def:INITIAL->1.8
config/i386/jit-i386.def:INITIAL->1.21
config/i386/jit3-i386.def:INITIAL->1.31
config/m68k/jit-m68k.def:INITIAL->1.10
config/m68k/jit3-m68k.def:INITIAL->1.13
config/powerpc/jit3-powerpc.def:1.6->1.7
config/sparc/jit-sparc.def:INITIAL->1.14
kaffe/kaffeh/mem.c:INITIAL->1.11
kaffe/kaffevm/baseClasses.c:INITIAL->1.63
kaffe/kaffevm/classMethod.c:1.140->1.141
kaffe/kaffevm/code-analyse.c:INITIAL->1.45
kaffe/kaffevm/exception.c:1.97->1.98
kaffe/kaffevm/external.c:INITIAL->1.81
kaffe/kaffevm/findInJar.c:INITIAL->1.67
kaffe/kaffevm/gcFuncs.c:1.71->1.72
kaffe/kaffevm/gtypes.h:INITIAL->1.16
kaffe/kaffevm/itypes.c:INITIAL->1.36
kaffe/kaffevm/jar.c:INITIAL->1.38
kaffe/kaffevm/kaffe.def:INITIAL->1.40
kaffe/kaffevm/readClass.c:INITIAL->1.25
kaffe/kaffevm/reference.c:1.6->1.7
kaffe/kaffevm/stackTrace.c:INITIAL->1.46
kaffe/kaffevm/support.c:INITIAL->1.83
kaffe/kaffevm/thread.c:1.96->1.97
kaffe/kaffevm/utf8const.c:1.48->1.49
kaffe/kaffevm/gcj/gcj-except.c:INITIAL->1.12
kaffe/kaffevm/intrp/machine.c:INITIAL->1.50
kaffe/kaffevm/jit/basecode.c:INITIAL->1.6
kaffe/kaffevm/jit/icode.c:INITIAL->1.34
kaffe/kaffevm/jit/labels.c:INITIAL->1.15
kaffe/kaffevm/jit/machine.c:INITIAL->1.80
kaffe/kaffevm/jit/registers.c:INITIAL->1.10
kaffe/kaffevm/jit3/basecode.c:INITIAL->1.11
kaffe/kaffevm/jit3/icode.c:1.52->1.53
kaffe/kaffevm/jit3/machine.c:1.74->1.75
kaffe/kaffevm/jit3/registers.c:INITIAL->1.21
kaffe/kaffevm/jni/jni.c:1.24->1.25
kaffe/kaffevm/kaffe-gc/gc-incremental.c:1.24->1.25
kaffe/kaffevm/kaffe-gc/gc-mem.c:1.27->1.28
kaffe/kaffevm/kaffe-gc/gc-refs.c:1.14->1.15
kaffe/kaffevm/systems/beos-native/signal.c:1.3->1.4
kaffe/kaffevm/systems/oskit-pthreads/signal.c:1.6->1.7
kaffe/kaffevm/systems/unix-pthreads/thread-impl.c:INITIAL->1.82
libraries/clib/native/Method.c:1.41->1.42
libraries/clib/native/Runtime.c:INITIAL->1.35
libraries/javalib/gnu/java/net/PlainSocketImpl.java:INITIAL->1.7
test/regression/InternHog.java:1.3->1.4
test/regression/SerialUID.java:1.1->1.2
Index: kaffe/ChangeLog
diff -u kaffe/ChangeLog:1.3966 kaffe/ChangeLog:1.3967
--- kaffe/ChangeLog:1.3966 Wed May 4 00:53:28 2005
+++ kaffe/ChangeLog Fri May 6 15:24:20 2005
@@ -1,3 +1,75 @@
+2005-05-04 Guilhem Lavaux <[EMAIL PROTECTED]>
+
+ * kaffe/kaffevm/classMethod.c,
+ (resolveInterfaces): Hold a strong reference on interfaces to
+ prevent it from being garbage collected before the destruction of
+ the class object.
+
+ * kaffe/kaffevm/gcFuncs.c
+ (destroyClass): Remove the strong reference.
+ (walkClass): Do not walk interfaces anymore as there is already a
+ strong reference on it.
+
+ * kaffe/kaffevm/utf8const.c
+ (utf8ConstInit): Symbol cleanup for kaffeh.
+
+ * kaffe/kaffevm/kaffe-gc/gc-refs.c
+ (KaffeGC_addWeakRef): Release the lock before going into malloc and
+ acquire it again after.
+
+ * kaffe/kaffevm/systems/unix-pthreads/thread-impl.c:
+ (jthread_exit) Fixed jthread_exit in case of unexpected error
+ returned by repsem_wait.
+
+ * config/sysdepCallMethod-ffi.h,
+ config/alpha/jit-alpha.def,
+ config/arm/jit3-arm.def,
+ config/i386/jit-i386.def,
+ config/i386/jit3-i386.def,
+ config/m68k/jit-m68k.def,
+ config/m68k/jit3-m68k.def,
+ config/powerpc/jit3-powerpc.def,
+ config/sparc/jit-sparc.def,
+ kaffe/kaffevm/baseClasses.c,
+ kaffe/kaffevm/classMethod.c,
+ kaffe/kaffevm/code-analyse.c,
+ kaffe/kaffevm/exception.c,
+ kaffe/kaffevm/external.c,
+ kaffe/kaffevm/findInJar.c,
+ kaffe/kaffevm/gtypes.h,
+ kaffe/kaffevm/itypes.c,
+ kaffe/kaffevm/jar.c,
+ kaffe/kaffevm/kaffe.def,
+ kaffe/kaffevm/reference.c,
+ kaffe/kaffevm/stackTrace.c,
+ kaffe/kaffevm/support.c,
+ kaffe/kaffevm/thread.c,
+ kaffe/kaffevm/gcj/gcj-except.c,
+ kaffe/kaffevm/intrp/machine.c,
+ kaffe/kaffevm/jit/basecode.c,
+ kaffe/kaffevm/jit/icode.c,
+ kaffe/kaffevm/jit/labels.c,
+ kaffe/kaffevm/jit/machine.c,
+ kaffe/kaffevm/jit/registers.c,
+ kaffe/kaffevm/jit3/basecode.c,
+ kaffe/kaffevm/jit3/icode.c,
+ kaffe/kaffevm/jit3/machine.c,
+ kaffe/kaffevm/jit3/registers.c,
+ kaffe/kaffevm/kaffe-gc/gc-incremental.c,
+ kaffe/kaffevm/kaffe-gc/gc-mem.c,
+ kaffe/kaffevm/systems/beos-native/signal.c,
+ kaffe/kaffevm/systems/oskit-pthreads/signal.c,
+ kaffe/kaffevm/systems/unix-pthreads/thread-impl.c,
+ libraries/clib/native/Method.c,
+ libraries/clib/native/Runtime.c: Renamed ABORT and EXIT to
+ KAFFEVM_ABORT and KAFFEVM_EXIT.
+
+ * libraries/javalib/gnu/java/net/PlainSocketImpl.java:
+ (connect) Imported internal checkings for socketConnect from GNU
Classpath.
+
+ * test/regression/SerialUID.java: Report the full stack trace of
+ the exception.
+
2005-05-03 Dalibor Topic <[EMAIL PROTECTED]>
* libraries/javalib/java/lang/ProcessInputStream.java: Removed,
Index: kaffe/config/sysdepCallMethod-ffi.h
diff -u kaffe/config/sysdepCallMethod-ffi.h:1.1
kaffe/config/sysdepCallMethod-ffi.h:1.2
--- kaffe/config/sysdepCallMethod-ffi.h:1.1 Fri Aug 27 12:22:03 2004
+++ kaffe/config/sysdepCallMethod-ffi.h Fri May 6 15:24:23 2005
@@ -62,7 +62,7 @@
ffi_call(&cif, (CALL)->function, (CALL)->ret, argvals); \
} \
else \
- ABORT(); \
+ KAFFEVM_ABORT();
\
} while (0);
#endif /* __sysdepCallMethod_ffi_h__ */
===================================================================
Checking out kaffe/config/alpha/jit-alpha.def
RCS: /home/cvs/kaffe/kaffe/config/alpha/jit-alpha.def,v
VERS: 1.14
***************
--- /dev/null Sun Aug 4 19:57:58 2002
+++ kaffe/config/alpha/jit-alpha.def Fri May 6 15:30:00 2005
@@ -0,0 +1,3252 @@
+/* jit-alpha.def
+ * Alpha instruction definition.
+ *
+ * Copyright (c) 1996, 1997
+ * Transvirtual Technologies, Inc. All rights reserved.
+ *
+ * See the file "license.terms" for information on usage and redistribution
+ * of this file.
+ */
+
+/* Turn this on for full denormal/NaN/Inf support at the expense of speed.
+ It is possible that this may be able to be turned off anyway on the
+ EV5 and higher, as they require no kernel support for such things. */
+
+/* If so, use IMPLVER to detect current AXP Implementation Version:
+ 0 21064 (EV4), 21064A (EV45), 21066A/21068A (LCA45)
+ 1 21164 (EV5), 21164A (EV56), 21164PC (PCA56)
+ 2 21264 (EV6)
+
+ Or AMASK bit 9: Support for precise arithmetic trap reporting in
+ hardware. The trap PC is the same as the instruction PC after the
+ traping instruction is executed.
+
+ See alpha_have_precise_trap(). Edouard */
+
+#define AXP_FULL_IEEE_FP
+
+#include <string.h>
+#include "classMethod.h"
+#include "access.h"
+#include "constpool.h"
+#include "exception.h"
+#include "thread.h"
+#include "gc.h"
+#include "gtypes.h"
+
+
+#define REG_v0 0
+#define REG_s0 9
+#define REG_fp 15
+#define REG_a0 16
+#define REG_t9 23
+#define REG_t10 24
+#define REG_t11 25
+#define REG_ra 26
+#define REG_pv 27
+#define REG_at 28
+#define REG_gp 29
+#define REG_sp 30
+#define REG_zero 31
+#define REG_f0 (32+0)
+#define REG_f2 (32+2)
+#define REG_fa0 (32+16)
+#define REG_ft (32+30)
+#define REG_fzero (32+31)
+
+
+#ifdef KAFFE_VMDEBUG
+static const char * const rnames[] = {
+ "v0",
+ "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
+ "s0", "s1", "s2", "s3", "s4", "s5",
+ "fp",
+ "a0", "a1", "a2", "a3", "a4", "a5",
+ "t8", "t9", "t10", "t11",
+ "ra",
+ "pv",
+ "at",
+ "gp",
+ "sp",
+ "zero",
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
+ "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
+ "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
+};
+
+#define regname(n) rnames[n]
+#define fregname(n) rnames[n]
+#endif
+
+int *alpha_slot2argoffset;
+int alpha_nslot2argoffset;
+alpha_jit_info_t alpha_jit_info;
+
+#define alpha_s32_rangecheck(v) ((v) >= -0x80000000L && (v) <
0x80000000L)
+
+
+/* --------------------------------------------------------------------- */
+/* Instruction formats */
+
+#define insn_bra(op, ra, disp) \
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | ((((disp) + 4) / 4) & 0x1FFFFF)))
+
+#define insn_mem(op, ra, rb, off) \
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | (((rb) & 0x1F) << 16) | ((off) & 0xFFFF)))
+
+#define insn_mfc(op, fn, ra, rb) \
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | (((rb) & 0x1F) << 16) | ((fn) & 0xFFFF)))
+
+#define insn_fp(op, fn, ra, rb, rc) \
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | (((rb) & 0x1F) << 16) | (((fn) & 0x7FF) << 5) \
+ | ((rc) & 0x1F)))
+
+#define insn_opr(op, fn, ra, rb, rc) \
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | (((rb) & 0x1F) << 16) | (((fn) & 0x7F) << 5) \
+ | ((rc) & 0x1F)))
+
+#define insn_oprl(op, fn, ra, lit, rc) \
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | (((lit) & 0xFF) << 13) | 0x1000 | (((fn) & 0x7F) << 5)\
+ | ((rc) & 0x1F)))
+
+#define insn_mbr(op, fn, ra, rb, extra)
\
+ LOUT((((op) << 26) | (((ra) & 0x1F) << 21) \
+ | (((rb) & 0x1F) << 16) | (((fn) & 3) << 14) \
+ | ((extra) & 0x3FFF)))
+
+
+/* --------------------------------------------------------------------- */
+/* Specific Instructions */
+
+#ifdef KAFFE_VMDEBUG
+int jit_debug;
+#define debug(x) (jit_debug ? dprintf("%x:\t", CODEPC), dprintf x : 0)
+#else
+#define debug(x)
+#endif
+
+#define op_addl(ra, rb, rc) \
+ debug(("addl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x00, (ra), (rb), (rc))
+
+#define op_addl_i(ra, ib, rc) \
+ debug(("addl\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x10, 0x00, (ra), (ib), (rc))
+
+#define op_addq(ra, rb, rc) \
+ debug(("addq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x20, (ra), (rb), (rc))
+
+#define op_addq_i(ra, ib, rc) \
+ debug(("addq\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x10, 0x20, (ra), (ib), (rc))
+
+#define op_adds(ra, rb, rc) \
+ debug(("adds\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x080, (ra), (rb), (rc))
+
+#define op_adds_su(ra, rb, rc) \
+ debug(("adds/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x580, (ra), (rb), (rc))
+
+#define op_addt(ra, rb, rc) \
+ debug(("addt\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0A0, (ra), (rb), (rc))
+
+#define op_addt_su(ra, rb, rc) \
+ debug(("addt/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x5A0, (ra), (rb), (rc))
+
+#define op_and(ra, rb, rc) \
+ debug(("and\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x11, 0x00, (ra), (rb), (rc))
+
+#define op_and_i(ra, ib, rc) \
+ debug(("and\t%s,%d,%s\n",regname(ra),(unsigned char)(ib),regname(rc)));
\
+ insn_oprl(0x11, 0x00, (ra), (ib), (rc))
+
+#define op_andnot_i(ra, ib, rc)
\
+ debug(("andnot\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x11, 0x08, (ra), (ib), (rc))
+
+#define op_beq(ra, disp) \
+ debug(("beq\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x39, (ra), (disp))
+
+#define op_bge(ra, disp) \
+ debug(("bge\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x3E, (ra), (disp))
+
+#define op_bgt(ra, disp) \
+ debug(("bgt\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x3F, (ra), (disp))
+
+#define op_ble(ra, disp) \
+ debug(("ble\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x3B, (ra), (disp))
+
+#define op_blt(ra, disp) \
+ debug(("blt\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x3A, (ra), (disp))
+
+#define op_bne(ra, disp) \
+ debug(("bne\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x3D, (ra), (disp))
+
+#define op_br(ra, disp)
\
+ debug(("br\t%s,%+d\n",regname(ra),(disp))); \
+ insn_bra(0x30, (ra), (disp))
+
+#define op_cmpeq(ra, rb, rc) \
+ debug(("cmpeq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x2D, (ra), (rb), (rc))
+
+#define op_cmpeq_i(ra, ib, rc) \
+ debug(("cmpeq\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x10, 0x2D, (ra), (ib), (rc))
+
+#define op_cmple(ra, rb, rc) \
+ debug(("cmple\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x6D, (ra), (rb), (rc))
+
+#define op_cmple_i(ra, ib, rc) \
+ debug(("cmple\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x10, 0x6D, (ra), (ib), (rc))
+
+#define op_cmplt(ra, rb, rc) \
+ debug(("cmplt\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x4D, (ra), (rb), (rc))
+
+#define op_cmplt_i(ra, ib, rc) \
+ debug(("cmplt\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x10, 0x4D, (ra), (ib), (rc))
+
+#define op_cmpult(ra, rb, rc) \
+ debug(("cmpult\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x1D, (ra), (rb), (rc))
+
+#define op_cmpult_i(ra, ib, rc)
\
+ debug(("cmpult\t%s,%d,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x10, 0x1D, (ra), (ib), (rc))
+
+#define op_cpysn(ra, rb, rc) \
+ debug(("cpysn\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x17, 0x021, (ra), (rb), (rc))
+
+#define op_cvtlq(rb, rc) \
+ debug(("cvtlq\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x17, 0x010, REG_zero, (rb), (rc))
+
+#define op_cvtql(rb, rc) \
+ debug(("cvtql\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x17, 0x030, REG_zero, (rb), (rc))
+
+#define op_cvtql_sv(rb, rc) \
+ debug(("cvtql/sv\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x17, 0x530, REG_zero, (rb), (rc))
+
+#define op_cvtqs(rb, rc) \
+ debug(("cvtqs\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0BC, REG_zero, (rb), (rc))
+
+#define op_cvtqt(rb, rc) \
+ debug(("cvtqt\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0BE, REG_zero, (rb), (rc))
+
+#define op_cvtst(rb, rc) \
+ debug(("cvtst\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x2AC, REG_zero, (rb), (rc))
+
+#define op_cvtst_s(rb, rc) \
+ debug(("cvtst/s\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x6AC, REG_zero, (rb), (rc))
+
+#define op_cvttq_c(rb, rc) \
+ debug(("cvttq/c\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x02F, REG_zero, (rb), (rc))
+
+#define op_cvttq_svc(rb, rc) \
+ debug(("cvttq/svc\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x52F, REG_zero, (rb), (rc))
+
+#define op_cvtts(rb, rc) \
+ debug(("cvtts\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0AC, REG_zero, (rb), (rc))
+
+#define op_cvtts_su(rb, rc) \
+ debug(("cvtts/su\t%s,%s\n",fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x5AC, REG_zero, (rb), (rc))
+
+#define op_divs(ra, rb, rc) \
+ debug(("divs\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x083, (ra), (rb), (rc))
+
+#define op_divs_su(ra, rb, rc) \
+ debug(("divs/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x583, (ra), (rb), (rc))
+
+#define op_divt(ra, rb, rc) \
+ debug(("divt\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0A3, (ra), (rb), (rc))
+
+#define op_divt_su(ra, rb, rc) \
+ debug(("divt/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x5A3, (ra), (rb), (rc))
+
+#define op_extbl(ra, rb, rc) \
+ debug(("extbl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x06, (ra), (rb), (rc))
+
+#define op_extwl(ra, rb, rc) \
+ debug(("extwl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x16, (ra), (rb), (rc))
+
+#define op_extqh(ra, rb, rc) \
+ debug(("extqh\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x7A, (ra), (rb), (rc))
+
+#define op_fmov(ra, rb)
\
+ debug(("fmov\t%s,%s\n",fregname(ra),fregname(rb))); \
+ insn_fp(0x17, 0x020, (ra), (ra), (rb))
+
+#define op_insbl(ra, rb, rc) \
+ debug(("insbl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x0B, (ra), (rb), (rc))
+
+#define op_inswl(ra, rb, rc) \
+ debug(("inswl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x1B, (ra), (rb), (rc))
+
+#define op_jmp(ra, rb, hint) \
+ debug(("jmp\t%s,(%s),%+d\n",regname(ra),regname(rb),(hint))); \
+ insn_mbr(0x1A, 0, (ra), (rb), (hint))
+
+#define op_jsr(ra, rb, hint) \
+ debug(("jsr\t%s,(%s),%+d\n",regname(ra),regname(rb),(hint))); \
+ insn_mbr(0x1A, 1, (ra), (rb), (hint))
+
+#define op_lda(ra, rb, off) \
+ debug(("lda\t%s,%hd(%s)\n",regname(ra),(short)(off),regname(rb))); \
+ insn_mem(0x08, (ra), (rb), (off))
+
+#define op_ldah(ra, rb, off) \
+ debug(("ldah\t%s,%hd(%s)\n",regname(ra),(short)(off),regname(rb))); \
+ insn_mem(0x09, (ra), (rb), (off))
+
+#define op_ldl(ra, rb, off) \
+ debug(("ldl\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x28, (ra), (rb), (off))
+
+#define op_ldq(ra, rb, off) \
+ debug(("ldq\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x29, (ra), (rb), (off))
+
+#define op_ldq_u(ra, rb, off) \
+ debug(("ldq_u\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x0B, (ra), (rb), (off))
+
+#define op_lds(ra, rb, off) \
+ debug(("lds\t%s,%hd(%s)\n",fregname(ra),(off),regname(rb))); \
+ insn_mem(0x22, (ra), (rb), (off))
+
+#define op_ldt(ra, rb, off) \
+ debug(("ldt\t%s,%hd(%s)\n",fregname(ra),(off),regname(rb))); \
+ insn_mem(0x23, (ra), (rb), (off))
+
+#define op_mov(ra, rb) \
+ debug(("mov\t%s,%s\n",regname(ra),regname(rb))); \
+ insn_opr(0x11, 0x20, (ra), (ra), (rb))
+
+#define op_mskbl(ra, rb, rc) \
+ debug(("mskbl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x02, (ra), (rb), (rc))
+
+#define op_mskwl(ra, rb, rc) \
+ debug(("mskwl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x12, (ra), (rb), (rc))
+
+#define op_mull(ra, rb, rc) \
+ debug(("mull\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x13, 0x00, (ra), (rb), (rc))
+
+#define op_mull_i(ra, ib, rc) \
+ debug(("mull\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_oprl(0x13, 0x00, (ra), (ib), (rc))
+
+#define op_mulq(ra, rb, rc) \
+ debug(("mulq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x13, 0x20, (ra), (rb), (rc))
+
+#define op_mulq_i(ra, ib, rc) \
+ debug(("mulq\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_opr(0x13, 0x20, (ra), (ib), (rc))
+
+#define op_muls(ra, rb, rc) \
+ debug(("muls\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x082, (ra), (rb), (rc))
+
+#define op_muls_su(ra, rb, rc) \
+ debug(("muls/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x582, (ra), (rb), (rc))
+
+#define op_mult(ra, rb, rc) \
+ debug(("mult\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0A2, (ra), (rb), (rc))
+
+#define op_mult_su(ra, rb, rc) \
+ debug(("mult/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x5A2, (ra), (rb), (rc))
+
+#define op_or(ra, rb, rc) \
+ debug(("or\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x11, 0x20, (ra), (rb), (rc))
+
+#define op_ret(ra, rb, code) \
+ debug(("ret\t%s,(%s),%d\n",regname(ra),regname(rb),(code))); \
+ insn_mbr(0x1A, 2, (ra), (rb), (code))
+
+#define op_s4addl(ra, rb, rc) \
+ debug(("s4addl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x02, (ra), (rb), (rc))
+
+#define op_s4addq(ra, rb, rc) \
+ debug(("s4addq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x22, (ra), (rb), (rc))
+
+#define op_s4subl(ra, rb, rc) \
+ debug(("s4subl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x0B, (ra), (rb), (rc))
+
+#define op_s4subq(ra, rb, rc) \
+ debug(("s4subq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x2B, (ra), (rb), (rc))
+
+#define op_s8addl(ra, rb, rc) \
+ debug(("s8addl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x12, (ra), (rb), (rc))
+
+#define op_s8addq(ra, rb, rc) \
+ debug(("s8addq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x32, (ra), (rb), (rc))
+
+#define op_s8subl(ra, rb, rc) \
+ debug(("s8subl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x1B, (ra), (rb), (rc))
+
+#define op_s8subq(ra, rb, rc) \
+ debug(("s8subq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x10, 0x3B, (ra), (rb), (rc))
+
+#define op_sll(ra, rb, rc) \
+ debug(("sll\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x39, (ra), (rb), (rc))
+
+#define op_sll_i(ra, ib, rc) \
+ debug(("sll\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_oprl(0x12, 0x39, (ra), (ib), (rc))
+
+#define op_sra(ra, rb, rc) \
+ debug(("sra\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x3C, (ra), (rb), (rc))
+
+#define op_sra_i(ra, ib, rc) \
+ debug(("sra\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_oprl(0x12, 0x3C, (ra), (ib), (rc))
+
+#define op_srl(ra, rb, rc) \
+ debug(("srl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x12, 0x34, (ra), (rb), (rc))
+
+#define op_srl_i(ra, ib, rc) \
+ debug(("srl\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_oprl(0x12, 0x34, (ra), (ib), (rc))
+
+#define op_stl(ra, rb, off) \
+ debug(("stl\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x2C, (ra), (rb), (off))
+
+#define op_stq(ra, rb, off) \
+ debug(("stq\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x2D, (ra), (rb), (off))
+
+#define op_stq_u(ra, rb, off) \
+ debug(("stq_u\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x0F, (ra), (rb), (off))
+
+#define op_sts(ra, rb, off) \
+ debug(("sts\t%s,%hd(%s)\n",fregname(ra),(off),regname(rb))); \
+ insn_mem(0x26, (ra), (rb), (off))
+
+#define op_stt(ra, rb, off) \
+ debug(("stt\t%s,%hd(%s)\n",fregname(ra),(off),regname(rb))); \
+ insn_mem(0x27, (ra), (rb), (off))
+
+#define op_subl(ra, rb, rc) \
+ debug(("subl\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc)));\
+ insn_opr(0x10, 0x09, (ra), (rb), (rc))
+
+#define op_subl_i(ra, ib, rc) \
+ debug(("subl\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_oprl(0x10, 0x09, (ra), (ib), (rc))
+
+#define op_subq(ra, rb, rc) \
+ debug(("subq\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc)));\
+ insn_opr(0x10, 0x29, (ra), (rb), (rc))
+
+#define op_subq_i(ra, ib, rc) \
+ debug(("subq\t%s,%d,%s\n",regname(ra),(ib),regname(rc))); \
+ insn_oprl(0x10, 0x29, (ra), (ib), (rc))
+
+#define op_subs(ra, rb, rc) \
+ debug(("subs\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x081, (ra), (rb), (rc))
+
+#define op_subs_su(ra, rb, rc) \
+ debug(("subs/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x581, (ra), (rb), (rc))
+
+#define op_subt(ra, rb, rc) \
+ debug(("subt\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc))); \
+ insn_fp(0x16, 0x0A1, (ra), (rb), (rc))
+
+#define op_subt_su(ra, rb, rc) \
+ debug(("subt/su\t%s,%s,%s\n",fregname(ra),fregname(rb),fregname(rc)));\
+ insn_fp(0x16, 0x5A1, (ra), (rb), (rc))
+
+#define op_trapb() \
+ debug(("trapb\n")); \
+ insn_mfc(0x18, 0x0000, 0, 0)
+
+#define op_unop() \
+ debug(("unop\n")); \
+ insn_mem(0x0B, REG_zero, REG_zero, 0)
+
+#define op_xor(ra, rb, rc) \
+ debug(("xor\t%s,%s,%s\n",regname(ra),regname(rb),regname(rc))); \
+ insn_opr(0x11, 0x40, (ra), (rb), (rc))
+
+#define op_zapnot_i(ra, ib, rc)
\
+ debug(("zapnot\t%s,%#x,%s\n",regname(ra),(unsigned
char)(ib),regname(rc))); \
+ insn_oprl(0x12, 0x31, (ra), (ib), (rc))
+
+
+/* The Byte-Word instruction extension present as of the EV56. */
+
+#define op_ldbu(ra, rb, off) \
+ debug(("ldbu\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x0A, (ra), (rb), (off))
+
+#define op_ldwu(ra, rb, off) \
+ debug(("ldwu\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x0C, (ra), (rb), (off))
+
+#define op_sextb(rb, rc) \
+ debug(("sextb\t%s,%s\n",regname(rb),regname(rc))); \
+ insn_opr(0x1C, 0x00, REG_zero, (rb), (rc))
+
+#define op_sextw(rb, rc) \
+ debug(("sextw\t%s,%s\n",regname(rb),regname(rc))); \
+ insn_opr(0x1C, 0x01, REG_zero, (rb), (rc))
+
+#define op_stb(ra, rb, off) \
+ debug(("stb\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x0E, (ra), (rb), (off))
+
+#define op_stw(ra, rb, off) \
+ debug(("stw\t%s,%hd(%s)\n",regname(ra),(off),regname(rb))); \
+ insn_mem(0x0D, (ra), (rb), (off))
+
+
+static inline long
+alpha_have_bwx(void)
+{
+#ifdef HAVE_ALPHA_ASM_AMASK
+ long r;
+ __asm__("amask 1,%0" : "=r"(r));
+#else
+ /* For those whose assemblers are so far behind not to
+ have the amask instruction. */
+ register long r __asm__("$0");
+ __asm__(".long %1"
+ : "=r"(r)
+ : "i"((0x11 << 26) | (REG_zero << 21) | (1 << 13)
+ | 0x1000 | (0x61 << 5) | REG_v0));
+#endif
+ return !r;
+}
+
+static inline long
+alpha_have_precise_trap(void)
+{
+#ifdef HAVE_ALPHA_ASM_AMASK
+ long r;
+ __asm__("amask %1,%0" : "=r"(r) : "r"(1<<9));
+#else
+ /* For those whose assemblers are so far behind not to
+ have the amask instruction. */
+ register long r __asm__("$0") = (1 << 9);
+ __asm__(".long %1"
+ : "=r"(r)
+ : "i"((0x11 << 26) | (REG_zero << 21) | (REG_v0 << 16)
+ | (0x61 << 5) | REG_v0));
+#endif
+ return !r;
+}
+
+
+/* --------------------------------------------------------------------- */
+/* Recognize constants that go to either and or zapnot. */
+
+static inline long
+alpha_zapnot_const(long x)
+{
+ /* Create a mask of bits in which bit n == 1 iff byte n == 0xFF. */
+ __asm__("cmpbge %1,%2,%0" : "=r"(x) : "r"(x), "r"(-1));
+ return x;
+}
+
+int
+alpha_andconst_rangecheck(long v)
+{
+ if (v >= 0 && v <= 0xFF) {
+ /* we can just use "and" */
+ return 1;
+ }
+ else if (~v >= 0 && ~v <= 0xFF) {
+ /* we can use "andnot" */
+ return 1;
+ }
+ else if ((alpha_zapnot_const(v) ^ alpha_zapnot_const(~v)) == 0xFF) {
+ /* we can use "zapnot" */
+ return 1;
+ }
+ return 0;
+}
+
+/* --------------------------------------------------------------------- */
+
+define_insn(unimplemented, unimplemented)
+{
+ KAFFEVM_ABORT();
+}
+
+define_insn(nop, nop)
+{
+ /* Presumably we're nop'ing for alignment not delay. */
+ op_unop();
+}
+
+static void
+alpha_ldgp(int reg)
+{
+ long hi, lo;
+
+ hi = -CODEPC;
+ lo = (short)hi;
+ hi = (hi - lo) >> 16;
+
+ if (hi) {
+ op_ldah(REG_gp, reg, hi);
+ op_lda(REG_gp, REG_gp, lo);
+ }
+ else {
+ op_lda(REG_gp, reg, lo);
+ }
+}
+
+/* --------------------------------------------------------------------- */
+
+define_insn(prologue, prologue_xxC)
+{
+ int r, N;
+ int l;
+ int sl;
+ int aspill;
+ label* L;
+ Method* meth;
+ int rsa_size;
+
+ L = const_label(1);
+ meth = const_method(2);
+
+#ifdef KAFFE_VMDEBUG
+ if (jit_debug) {
+ dprintf("\n%s.%s %s\n", meth->class->name->data,
+ meth->name->data, METHOD_SIGD(meth));
+ }
+#endif
+ alpha_jit_info.ieee = 0;
+
+ /* Initial stack frame looks like:
+ *
+ * | Argument above 6 |
+ * SP-> |-------------------------------|
+ *
+ * Calling Standard for Alpha Systems
+ * 3.1.2.1 Stack Frame Format
+ *
+ * Figure 3-1: Fixed Size Stack Frame Format
+ * (PDSC_FLAGS_BASE_REG_IS_FP is 0)
+ * octaword-aligned
+ * | Argument above 6 |
+ * |-------------------------------| <- PDSC_RPD_FRAME_SIZE from SP
+ * | Argument home area |
+ * |- - - - - - - - - - - - - - - -|
+ * | Fixed temporary locations |
+ * |-------------------------------|
+ * | Register save area |
+ * |-------------------------------| <- PDSC_RPD_RSA_OFFSET from SP
+ * | Fixed temporary locations |
+ * |-------------------------------| <- SP
+ *
+ * Figure 3-2: Variable Size Stack Frame Format
+ * (PDSC_FLAGS_BASE_REG_IS_FP is 1)
+ * octaword-aligned
+ * | Argument above 6 |
+ * |-------------------------------| <- PDSC_RPD_FRAME_SIZE from FP
+ * | Argument home area |
+ * |- - - - - - - - - - - - - - - -|
+ * | Fixed temporary locations |
+ * |-------------------------------|
+ * | Register save area |
+ * |-------------------------------| <- PDSC_RPD_RSA_OFFSET from FP
+ * | Fixed temporary locations |
+ * |-------------------------------| <- FP
+ * | Stack temporary area |
+ * |-------------------------------| <- SP
+ *
+ * * Fixed temporary locations are optional sections. These locations
+ * might include, for exemple, register spill areas, ..., or fixed
+ * temporary locations.
+ *
+ * * The argument home area is an optionl section, it is a region of
+ * memory used by the called procedure for the purpose of assembling
+ * in contignous memory the arguments passed in registers adjacent to
+ * the arguments passed in memory, so that all argument can be
+ * addressed as a contignous array.
+ *
+ * * The register save area is the set of consecutive quadwords where
+ * the current procedure saves and restores registers. The registers
+ * save area begins at the location pointed to by the frame base
+ * register (as indicated by PDSC_FLAGS_BASE_REG_IS_FP) added to the
+ * value of the content of PDSC_RPD_RSA_OFFSET. The result must be
+ * a quadword-aligned address.
+ *
+ * All registers saved in the variable portion of the register save
+ * area must have the corresponding bit set to 1 in the appropriate
+ * procedure descriptor register save mask. The algorithm for
+ * packing saved register in the quadword-aligned register save area
+ * is as follows:
+ * . The return address is save at the lowest address of the
+ * register save area, offset 0.
+ * . All saved integer registers, as indicated by the corresponding
+ * bit in PDSC_RPD_IMASK being set to 1, are store, in register
+ * order, in consecutive quadwords beginning at offset 8 of the
+ * register save area.
+ * . All saved floating-point registers, as indicated by the
+ * corresponding bit in PDSC_RPD_FMASK being set to 1, are stored,
+ * in register-number order, in consecutive quadwords following
+ * the saved integer registers.
+ *
+ * A standard-conforming procedure that utilizes a register save area
+ * must save the return address register at offset 0 in the register
+ * save area. There is no corresponding bit in the register save
+ * mask for this register slot.
+ *
+ *
+ * Applied for JIT Stack Frame:
+ * We use a fixed-stack frame (PDSC_FLAGS_BASE_REG_IS_FP is 0) with
+ * FP used as a virtual frame pointer to improve FRAMEOBJECT() macro.
+ *
+ * | Argument above 6 |
*** Patch too long, truncated ***
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