In the Rules.make file in both 2.4.18 and 2.5.7 kernels, the rule to
make a .c into a .o looks like this:
%.o: %.c
$(CC) $(CFLAGS) [stuff deleted] -c -o $@ $<
The rule to build a .c into .o when the .o happens to be in
$(export-objs) looks like this:
$(export-objs): $(export-objs:.o=.c) [ deleted ]
$(CC) $(CFLAGS) [stuff deleted] -DEXPORT_SYMTAB -c $(@:.o=.c)
Notice that the export-objs rule is missing a "-o" flag to the compiler.
This means that if my module's Makefile needs to get some files out a a
subdirectory, say "extrastuff/extra.c", and I put "extrastuff/extra.o"
in $(obj-m), then the compiler will put the .o in the extrastuff
subdirectory as "extrastuff/extra.o". But if that file is in the
$(exports-objs) list, then
the compiler, missing any -o option, will put the output in "extra.o".
It seems wrong to me that the .o is left in a different position based
on whether it has exported symbols or not. Was this just an oversight,
and no one has ever happened to have a subdirectory in their module
directory, or is there some reason that Rules.make is written the way
that it is?
By the way, I changed the export-objs rule to look like "-c -o $@
$(@:.o=.c)" at the end, and the kernel and modules and my module seemed
to compile fine.
Thanks,
Wesley Smith
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