[ It's weird to have a 64 bit offset into anything but the code is very
  consistent about this.  The comments mention that often the values are
  less that PAGE_SIZE.  My guess is that the type should be changed to
  u32, but if we don't do that, then we should at least silence the
  static checker warning by casting the shift.  - dan ]

tree:   git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git master
head:   395eea6ccf2b253f81b4718ffbcae67d36fe2e69
commit: e85c9a7abfa407ed99f8516cf6a10d397247315a [1404/1409] cxgb4/cxgb4vf: Add 
code to calculate T5 BAR2 Offsets for SGE Queue Registers

drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c:489 t4_bar2_sge_qregs() warn: 
should '(qid >> qpp_shift) << page_shift' be a 64 bit type?
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c:4062 t4_bar2_sge_qregs() warn: 
should '(qid >> qpp_shift) << page_shift' be a 64 bit type?

git remote add net-next 
git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
git remote update net-next
git checkout e85c9a7abfa407ed99f8516cf6a10d397247315a
vim +489 drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c

e85c9a7a Hariprasad Shenai 2014-12-03  473       */
e85c9a7a Hariprasad Shenai 2014-12-03  474      page_shift = 
adapter->params.sge.sge_vf_hps + 10;
e85c9a7a Hariprasad Shenai 2014-12-03  475      page_size = 1 << page_shift;
e85c9a7a Hariprasad Shenai 2014-12-03  476  
e85c9a7a Hariprasad Shenai 2014-12-03  477      /* Get the right Queues per 
Page parameters for our Queue.
e85c9a7a Hariprasad Shenai 2014-12-03  478       */
e85c9a7a Hariprasad Shenai 2014-12-03  479      qpp_shift = (qtype == 
T4_BAR2_QTYPE_EGRESS
e85c9a7a Hariprasad Shenai 2014-12-03  480                   ? 
adapter->params.sge.sge_vf_eq_qpp
e85c9a7a Hariprasad Shenai 2014-12-03  481                   : 
adapter->params.sge.sge_vf_iq_qpp);
e85c9a7a Hariprasad Shenai 2014-12-03  482      qpp_mask = (1 << qpp_shift) - 1;
e85c9a7a Hariprasad Shenai 2014-12-03  483  
e85c9a7a Hariprasad Shenai 2014-12-03  484      /* Calculate the basics of the 
BAR2 SGE Queue register area:
e85c9a7a Hariprasad Shenai 2014-12-03  485       *  o The BAR2 page the Queue 
registers will be in.
e85c9a7a Hariprasad Shenai 2014-12-03  486       *  o The BAR2 Queue ID.
e85c9a7a Hariprasad Shenai 2014-12-03  487       *  o The BAR2 Queue ID Offset 
into the BAR2 page.
e85c9a7a Hariprasad Shenai 2014-12-03  488       */
e85c9a7a Hariprasad Shenai 2014-12-03 @489      bar2_page_offset = ((qid >> 
qpp_shift) << page_shift);
e85c9a7a Hariprasad Shenai 2014-12-03  490      bar2_qid = qid & qpp_mask;
e85c9a7a Hariprasad Shenai 2014-12-03  491      bar2_qid_offset = bar2_qid * 
SGE_UDB_SIZE;
e85c9a7a Hariprasad Shenai 2014-12-03  492  
e85c9a7a Hariprasad Shenai 2014-12-03  493      /* If the BAR2 Queue ID Offset 
is less than the Page Size, then the
e85c9a7a Hariprasad Shenai 2014-12-03  494       * hardware will infer the 
Absolute Queue ID simply from the writes to
e85c9a7a Hariprasad Shenai 2014-12-03  495       * the BAR2 Queue ID Offset 
within the BAR2 Page (and we need to use a
e85c9a7a Hariprasad Shenai 2014-12-03  496       * BAR2 Queue ID of 0 for those 
writes).  Otherwise, we'll simply
e85c9a7a Hariprasad Shenai 2014-12-03  497       * write to the first BAR2 SGE 
Queue Area within the BAR2 Page with

---
0-DAY kernel test infrastructure                Open Source Technology Center
http://lists.01.org/mailman/listinfo/kbuild                 Intel Corporation
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