CC: [email protected] TO: Colin Xu <[email protected]> CC: "Qin, Chao" <[email protected]> CC: Hang Yuan <[email protected]>
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto head: 8bbfe55bfdb2905c35914605bc1b4a4404d86649 commit: 2521b097a48688b899e3db9cb855aa1ec59b02e8 [8/24] drm/i915/gvt: Rebase IDV 2.1 direct display to 5.4.x. :::::: branch date: 4 months ago :::::: commit date: 4 months ago config: x86_64-randconfig-m001-20201026 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> New smatch warnings: drivers/gpu/drm/i915/intel_pm.c:4004 skl_ddb_get_hw_plane_state() warn: variable dereferenced before check 'gvt' (see line 3994) drivers/gpu/drm/i915/intel_pm.c:4336 skl_allocate_pipe_ddb() warn: variable dereferenced before check 'gvt' (see line 4297) drivers/gpu/drm/i915/display/intel_display.c:10518 skylake_get_initial_plane_config() warn: variable dereferenced before check 'gvt' (see line 10498) drivers/gpu/drm/i915/display/intel_display.c:11871 i9xx_cursor_get_hw_state() warn: variable dereferenced before check 'gvt' (see line 11869) drivers/gpu/drm/i915/display/intel_sprite.c:636 skl_program_plane() warn: variable dereferenced before check 'gvt' (see line 608) drivers/gpu/drm/i915/display/intel_sprite.c:786 skl_plane_get_hw_state() warn: variable dereferenced before check 'gvt' (see line 784) drivers/gpu/drm/i915/gvt/display.c:293 emulate_monitor_status_change() warn: curly braces intended? drivers/gpu/drm/i915/gvt/display.c:296 emulate_monitor_status_change() warn: inconsistent indenting drivers/gpu/drm/i915/gvt/display.c:320 emulate_monitor_status_change() error: buffer overflow 'bdw_hpd_pin' 4 <= 4 drivers/gpu/drm/i915/gvt/display.c:329 emulate_monitor_status_change() error: buffer overflow 'bxt_hpd_pin' 3 <= 4 drivers/gpu/drm/i915/gvt/display.c:1022 intel_vgpu_init_display() error: 'vgpu' dereferencing possible ERR_PTR() drivers/gpu/drm/i915/gvt/display.c:2232 intel_gvt_store_vgpu_display_owner() warn: should '(1 << port)' be a 64 bit type? Old smatch warnings: drivers/gpu/drm/i915/intel_pm.c:4020 skl_ddb_get_hw_plane_state() warn: variable dereferenced before check 'gvt' (see line 3994) drivers/gpu/drm/i915/intel_pm.c:4089 skl_pipe_ddb_get_hw_state() warn: inconsistent indenting drivers/gpu/drm/i915/display/intel_display.c:6136 skl_update_scaler_plane() error: we previously assumed 'fb' could be null (see line 6121) drivers/gpu/drm/i915/gvt/display.c:1040 intel_vgpu_init_display() error: 'vgpu' dereferencing possible ERR_PTR() vim +/gvt +4004 drivers/gpu/drm/i915/intel_pm.c a269c5839bc4e3 Damien Lespiau 2014-11-04 3982 ddf343191420e8 Mahesh Kumar 2018-04-09 3983 static void ddf343191420e8 Mahesh Kumar 2018-04-09 3984 skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, ddf343191420e8 Mahesh Kumar 2018-04-09 3985 const enum pipe pipe, ddf343191420e8 Mahesh Kumar 2018-04-09 3986 const enum plane_id plane_id, ff43bc379e16c9 Ville Syrjälä 2018-11-27 3987 struct skl_ddb_entry *ddb_y, ff43bc379e16c9 Ville Syrjälä 2018-11-27 3988 struct skl_ddb_entry *ddb_uv) ddf343191420e8 Mahesh Kumar 2018-04-09 3989 { ff43bc379e16c9 Ville Syrjälä 2018-11-27 3990 u32 val, val2; ff43bc379e16c9 Ville Syrjälä 2018-11-27 3991 u32 fourcc = 0; 2521b097a48688 Colin Xu 2020-04-14 3992 #if IS_ENABLED(CONFIG_DRM_I915_GVT) 2521b097a48688 Colin Xu 2020-04-14 3993 struct intel_gvt *gvt = dev_priv->gvt; 2521b097a48688 Colin Xu 2020-04-14 @3994 struct intel_gvt_pipe_info *pipe_info = &gvt->pipe_info[pipe]; 2521b097a48688 Colin Xu 2020-04-14 3995 struct intel_dom0_plane_regs *dom0_regs = 2521b097a48688 Colin Xu 2020-04-14 3996 &gvt->pipe_info[pipe].plane_info[plane_id].dom0_regs; 2521b097a48688 Colin Xu 2020-04-14 3997 #endif ddf343191420e8 Mahesh Kumar 2018-04-09 3998 ddf343191420e8 Mahesh Kumar 2018-04-09 3999 /* Cursor doesn't support NV12/planar, so no extra calculation needed */ ddf343191420e8 Mahesh Kumar 2018-04-09 4000 if (plane_id == PLANE_CURSOR) { ddf343191420e8 Mahesh Kumar 2018-04-09 4001 val = I915_READ(CUR_BUF_CFG(pipe)); 2521b097a48688 Colin Xu 2020-04-14 4002 #if IS_ENABLED(CONFIG_DRM_I915_GVT) 2521b097a48688 Colin Xu 2020-04-14 4003 /* In GVT direct display, we only use the statically allocated ddb */ 2521b097a48688 Colin Xu 2020-04-14 @4004 if (gvt) { 2521b097a48688 Colin Xu 2020-04-14 4005 struct skl_ddb_entry *ddb_y = &pipe_info->ddb_y[PLANE_CURSOR]; 2521b097a48688 Colin Xu 2020-04-14 4006 2521b097a48688 Colin Xu 2020-04-14 4007 if (ddb_y->end) 2521b097a48688 Colin Xu 2020-04-14 4008 val = (ddb_y->end - 1) << 16 | ddb_y->start; 2521b097a48688 Colin Xu 2020-04-14 4009 else 2521b097a48688 Colin Xu 2020-04-14 4010 val = 0; 2521b097a48688 Colin Xu 2020-04-14 4011 } 2521b097a48688 Colin Xu 2020-04-14 4012 #endif ff43bc379e16c9 Ville Syrjälä 2018-11-27 4013 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); ddf343191420e8 Mahesh Kumar 2018-04-09 4014 return; ddf343191420e8 Mahesh Kumar 2018-04-09 4015 } ddf343191420e8 Mahesh Kumar 2018-04-09 4016 ddf343191420e8 Mahesh Kumar 2018-04-09 4017 val = I915_READ(PLANE_CTL(pipe, plane_id)); 2521b097a48688 Colin Xu 2020-04-14 4018 #if IS_ENABLED(CONFIG_DRM_I915_GVT) 2521b097a48688 Colin Xu 2020-04-14 4019 // If pipe is not owned by host, read plane_ctl from cache 2521b097a48688 Colin Xu 2020-04-14 4020 if (gvt && gvt->pipe_info[pipe].plane_info[plane_id].owner) 2521b097a48688 Colin Xu 2020-04-14 4021 val = dom0_regs->plane_ctl; 2521b097a48688 Colin Xu 2020-04-14 4022 #endif ddf343191420e8 Mahesh Kumar 2018-04-09 4023 ddf343191420e8 Mahesh Kumar 2018-04-09 4024 /* No DDB allocated for disabled planes */ ff43bc379e16c9 Ville Syrjälä 2018-11-27 4025 if (val & PLANE_CTL_ENABLE) ff43bc379e16c9 Ville Syrjälä 2018-11-27 4026 fourcc = skl_format_to_fourcc(val & PLANE_CTL_FORMAT_MASK, ddf343191420e8 Mahesh Kumar 2018-04-09 4027 val & PLANE_CTL_ORDER_RGBX, ddf343191420e8 Mahesh Kumar 2018-04-09 4028 val & PLANE_CTL_ALPHA_MASK); ddf343191420e8 Mahesh Kumar 2018-04-09 4029 ff43bc379e16c9 Ville Syrjälä 2018-11-27 4030 if (INTEL_GEN(dev_priv) >= 11) { ff43bc379e16c9 Ville Syrjälä 2018-11-27 4031 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); ff43bc379e16c9 Ville Syrjälä 2018-11-27 4032 skl_ddb_entry_init_from_hw(dev_priv, ddb_y, val); ff43bc379e16c9 Ville Syrjälä 2018-11-27 4033 } else { ddf343191420e8 Mahesh Kumar 2018-04-09 4034 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); ddf343191420e8 Mahesh Kumar 2018-04-09 4035 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id)); ddf343191420e8 Mahesh Kumar 2018-04-09 4036 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected]
.config.gz
Description: application/gzip
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