CC: [email protected] TO: Colin Xu <[email protected]> CC: "Qin, Chao" <[email protected]>
tree: https://github.com/intel/linux-intel-lts.git 5.4/yocto head: 8bbfe55bfdb2905c35914605bc1b4a4404d86649 commit: 0e3b0949baf42ea222b22bc5c7fb1e8c4695ebbb [16/24] drm/i915/gvt: Handle split gamma mode for direct display :::::: branch date: 4 months ago :::::: commit date: 4 months ago config: x86_64-randconfig-m001-20201026 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> New smatch warnings: drivers/gpu/drm/i915/display/intel_color.c:704 bdw_load_lut_10() warn: variable dereferenced before check 'gvt' (see line 687) Old smatch warnings: drivers/gpu/drm/i915/display/intel_color.c:1761 i9xx_read_lut_8() error: potential null dereference 'blob'. (drm_property_create_blob returns null) drivers/gpu/drm/i915/display/intel_color.c:1805 i965_read_lut_10p6() error: potential null dereference 'blob'. (drm_property_create_blob returns null) drivers/gpu/drm/i915/display/intel_color.c:1857 chv_read_cgm_lut() error: potential null dereference 'blob'. (drm_property_create_blob returns null) drivers/gpu/drm/i915/display/intel_color.c:1899 ilk_read_lut_10() error: potential null dereference 'blob'. (drm_property_create_blob returns null) drivers/gpu/drm/i915/display/intel_color.c:1946 glk_read_lut_10() error: potential null dereference 'blob'. (drm_property_create_blob returns null) vim +/gvt +704 drivers/gpu/drm/i915/display/intel_color.c c21ce2effc5278d drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 674 c21ce2effc5278d drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 675 /* On BDW+ the index auto increment mode actually works */ 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 676 static void bdw_load_lut_10(struct intel_crtc *crtc, 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 677 const struct drm_property_blob *blob, 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 678 u32 prec_index) 82cf435b3134a5f drivers/gpu/drm/i915/intel_color.c Lionel Landwerlin 2016-03-16 679 { 23b03a272c2beed drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-02-05 680 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 681 int hw_lut_size = ivb_lut_10_size(prec_index); 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 682 const struct drm_color_lut *lut = blob->data; 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 683 int i, lut_size = drm_color_lut_size(blob); 23b03a272c2beed drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-02-05 684 enum pipe pipe = crtc->pipe; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 685 #if IS_ENABLED(CONFIG_DRM_I915_GVT) 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 686 struct intel_gvt *gvt = dev_priv->gvt; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 @687 struct intel_dom0_pipe_regs *pipe_regs = &gvt->pipe_info[pipe].dom0_pipe_regs; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 688 struct prec_pal_data *pal_data = NULL; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 689 if (prec_index & PAL_PREC_SPLIT_MODE) 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 690 pal_data = pipe_regs->prec_palette_split; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 691 else 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 692 pal_data = pipe_regs->prec_palette_nonsplit; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 693 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 694 for (i = 0; i < hw_lut_size; i++) { 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 695 /* We discard half the user entries in split gamma mode */ 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 696 const struct drm_color_lut *entry = 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 697 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 698 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 699 // No need set dirty bit here since all set in d0_regs. 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 700 pal_data[prec_index + i].val = ilk_lut_10(entry); 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 701 //pal_data[prec_index + i].dirty = 1; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 702 } 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 703 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 @704 if (gvt && gvt->pipe_info[pipe].owner) 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 705 return; 0e3b0949baf42ea drivers/gpu/drm/i915/display/intel_color.c Colin Xu 2020-05-09 706 #endif 82cf435b3134a5f drivers/gpu/drm/i915/intel_color.c Lionel Landwerlin 2016-03-16 707 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 708 I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 709 PAL_PREC_AUTO_INCREMENT); 82cf435b3134a5f drivers/gpu/drm/i915/intel_color.c Lionel Landwerlin 2016-03-16 710 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 711 for (i = 0; i < hw_lut_size; i++) { 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 712 /* We discard half the user entries in split gamma mode */ 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 713 const struct drm_color_lut *entry = 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 714 &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 715 795f672b88ba4a6 drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-03 716 I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry)); 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 717 } 82cf435b3134a5f drivers/gpu/drm/i915/intel_color.c Lionel Landwerlin 2016-03-16 718 61eae851c92b0b5 drivers/gpu/drm/i915/intel_color.c Uma Shankar 2019-03-29 719 /* 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 720 * Reset the index, otherwise it prevents the legacy palette to be 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 721 * written properly. 502da13a72dad49 drivers/gpu/drm/i915/intel_color.c Uma Shankar 2019-03-29 722 */ 5bda1aca5d9475e drivers/gpu/drm/i915/intel_color.c Ville Syrjälä 2019-04-01 723 I915_WRITE(PREC_PAL_INDEX(pipe), 0); 502da13a72dad49 drivers/gpu/drm/i915/intel_color.c Uma Shankar 2019-03-29 724 } 82cf435b3134a5f drivers/gpu/drm/i915/intel_color.c Lionel Landwerlin 2016-03-16 725 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected]
.config.gz
Description: application/gzip
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