CC: [email protected] In-Reply-To: <[email protected]> References: <[email protected]> TO: Ard Biesheuvel <[email protected]> TO: [email protected] CC: [email protected] CC: [email protected] CC: [email protected] CC: Ard Biesheuvel <[email protected]> CC: Nick Desaulniers <[email protected]> CC: Arvind Sankar <[email protected]> CC: Randy Dunlap <[email protected]> CC: Josh Poimboeuf <[email protected]> CC: Thomas Gleixner <[email protected]>
Hi Ard, I love your patch! Perhaps something to improve: [auto build test WARNING on bpf-next/master] [also build test WARNING on bpf/master linus/master linux/master v5.10-rc1 next-20201028] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/0day-ci/linux/commits/Ard-Biesheuvel/bpf-don-t-rely-on-GCC-__attribute__-optimize-to-disable-GCSE/20201029-060312 base: https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git master :::::: branch date: 6 hours ago :::::: commit date: 6 hours ago config: i386-randconfig-m021-20201028 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> smatch warnings: kernel/bpf/interp.c:277 ___bpf_prog_run() warn: should 'regs[insn->dst_reg] << regs[insn->src_reg]' be a 64 bit type? kernel/bpf/interp.c:277 ___bpf_prog_run() warn: should 'regs[insn->dst_reg] << insn->imm' be a 64 bit type? vim +277 kernel/bpf/interp.c 11087cf7f27f46 Ard Biesheuvel 2020-10-28 254 11087cf7f27f46 Ard Biesheuvel 2020-10-28 255 select_insn: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 256 goto *jumptable[insn->code]; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 257 11087cf7f27f46 Ard Biesheuvel 2020-10-28 258 /* ALU */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 259 #define ALU(OPCODE, OP) \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 260 ALU64_##OPCODE##_X: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 261 DST = DST OP SRC; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 262 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 263 ALU_##OPCODE##_X: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 264 DST = (u32) DST OP (u32) SRC; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 265 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 266 ALU64_##OPCODE##_K: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 267 DST = DST OP IMM; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 268 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 269 ALU_##OPCODE##_K: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 270 DST = (u32) DST OP (u32) IMM; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 271 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 272 11087cf7f27f46 Ard Biesheuvel 2020-10-28 273 ALU(ADD, +) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 274 ALU(SUB, -) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 275 ALU(AND, &) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 276 ALU(OR, |) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 @277 ALU(LSH, <<) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 278 ALU(RSH, >>) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 279 ALU(XOR, ^) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 280 ALU(MUL, *) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 281 #undef ALU 11087cf7f27f46 Ard Biesheuvel 2020-10-28 282 ALU_NEG: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 283 DST = (u32) -DST; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 284 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 285 ALU64_NEG: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 286 DST = -DST; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 287 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 288 ALU_MOV_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 289 DST = (u32) SRC; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 290 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 291 ALU_MOV_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 292 DST = (u32) IMM; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 293 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 294 ALU64_MOV_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 295 DST = SRC; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 296 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 297 ALU64_MOV_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 298 DST = IMM; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 299 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 300 LD_IMM_DW: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 301 DST = (u64) (u32) insn[0].imm | ((u64) (u32) insn[1].imm) << 32; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 302 insn++; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 303 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 304 ALU_ARSH_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 305 DST = (u64) (u32) (((s32) DST) >> SRC); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 306 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 307 ALU_ARSH_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 308 DST = (u64) (u32) (((s32) DST) >> IMM); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 309 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 310 ALU64_ARSH_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 311 (*(s64 *) &DST) >>= SRC; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 312 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 313 ALU64_ARSH_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 314 (*(s64 *) &DST) >>= IMM; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 315 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 316 ALU64_MOD_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 317 div64_u64_rem(DST, SRC, &AX); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 318 DST = AX; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 319 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 320 ALU_MOD_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 321 AX = (u32) DST; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 322 DST = do_div(AX, (u32) SRC); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 323 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 324 ALU64_MOD_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 325 div64_u64_rem(DST, IMM, &AX); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 326 DST = AX; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 327 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 328 ALU_MOD_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 329 AX = (u32) DST; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 330 DST = do_div(AX, (u32) IMM); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 331 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 332 ALU64_DIV_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 333 DST = div64_u64(DST, SRC); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 334 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 335 ALU_DIV_X: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 336 AX = (u32) DST; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 337 do_div(AX, (u32) SRC); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 338 DST = (u32) AX; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 339 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 340 ALU64_DIV_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 341 DST = div64_u64(DST, IMM); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 342 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 343 ALU_DIV_K: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 344 AX = (u32) DST; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 345 do_div(AX, (u32) IMM); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 346 DST = (u32) AX; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 347 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 348 ALU_END_TO_BE: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 349 switch (IMM) { 11087cf7f27f46 Ard Biesheuvel 2020-10-28 350 case 16: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 351 DST = (__force u16) cpu_to_be16(DST); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 352 break; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 353 case 32: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 354 DST = (__force u32) cpu_to_be32(DST); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 355 break; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 356 case 64: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 357 DST = (__force u64) cpu_to_be64(DST); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 358 break; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 359 } 11087cf7f27f46 Ard Biesheuvel 2020-10-28 360 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 361 ALU_END_TO_LE: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 362 switch (IMM) { 11087cf7f27f46 Ard Biesheuvel 2020-10-28 363 case 16: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 364 DST = (__force u16) cpu_to_le16(DST); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 365 break; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 366 case 32: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 367 DST = (__force u32) cpu_to_le32(DST); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 368 break; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 369 case 64: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 370 DST = (__force u64) cpu_to_le64(DST); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 371 break; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 372 } 11087cf7f27f46 Ard Biesheuvel 2020-10-28 373 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 374 11087cf7f27f46 Ard Biesheuvel 2020-10-28 375 /* CALL */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 376 JMP_CALL: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 377 /* Function call scratches BPF_R1-BPF_R5 registers, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 378 * preserves BPF_R6-BPF_R9, and stores return value 11087cf7f27f46 Ard Biesheuvel 2020-10-28 379 * into BPF_R0. 11087cf7f27f46 Ard Biesheuvel 2020-10-28 380 */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 381 BPF_R0 = (__bpf_call_base + insn->imm)(BPF_R1, BPF_R2, BPF_R3, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 382 BPF_R4, BPF_R5); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 383 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 384 11087cf7f27f46 Ard Biesheuvel 2020-10-28 385 JMP_CALL_ARGS: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 386 BPF_R0 = (__bpf_call_base_args + insn->imm)(BPF_R1, BPF_R2, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 387 BPF_R3, BPF_R4, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 388 BPF_R5, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 389 insn + insn->off + 1); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 390 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 391 11087cf7f27f46 Ard Biesheuvel 2020-10-28 392 JMP_TAIL_CALL: { 11087cf7f27f46 Ard Biesheuvel 2020-10-28 393 struct bpf_map *map = (struct bpf_map *) (unsigned long) BPF_R2; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 394 struct bpf_array *array = container_of(map, struct bpf_array, map); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 395 struct bpf_prog *prog; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 396 u32 index = BPF_R3; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 397 11087cf7f27f46 Ard Biesheuvel 2020-10-28 398 if (unlikely(index >= array->map.max_entries)) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 399 goto out; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 400 if (unlikely(tail_call_cnt > MAX_TAIL_CALL_CNT)) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 401 goto out; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 402 11087cf7f27f46 Ard Biesheuvel 2020-10-28 403 tail_call_cnt++; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 404 11087cf7f27f46 Ard Biesheuvel 2020-10-28 405 prog = READ_ONCE(array->ptrs[index]); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 406 if (!prog) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 407 goto out; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 408 11087cf7f27f46 Ard Biesheuvel 2020-10-28 409 /* ARG1 at this point is guaranteed to point to CTX from 11087cf7f27f46 Ard Biesheuvel 2020-10-28 410 * the verifier side due to the fact that the tail call is 11087cf7f27f46 Ard Biesheuvel 2020-10-28 411 * handled like a helper, that is, bpf_tail_call_proto, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 412 * where arg1_type is ARG_PTR_TO_CTX. 11087cf7f27f46 Ard Biesheuvel 2020-10-28 413 */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 414 insn = prog->insnsi; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 415 goto select_insn; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 416 out: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 417 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 418 } 11087cf7f27f46 Ard Biesheuvel 2020-10-28 419 JMP_JA: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 420 insn += insn->off; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 421 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 422 JMP_EXIT: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 423 return BPF_R0; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 424 /* JMP */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 425 #define COND_JMP(SIGN, OPCODE, CMP_OP) \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 426 JMP_##OPCODE##_X: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 427 if ((SIGN##64) DST CMP_OP (SIGN##64) SRC) { \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 428 insn += insn->off; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 429 CONT_JMP; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 430 } \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 431 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 432 JMP32_##OPCODE##_X: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 433 if ((SIGN##32) DST CMP_OP (SIGN##32) SRC) { \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 434 insn += insn->off; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 435 CONT_JMP; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 436 } \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 437 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 438 JMP_##OPCODE##_K: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 439 if ((SIGN##64) DST CMP_OP (SIGN##64) IMM) { \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 440 insn += insn->off; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 441 CONT_JMP; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 442 } \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 443 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 444 JMP32_##OPCODE##_K: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 445 if ((SIGN##32) DST CMP_OP (SIGN##32) IMM) { \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 446 insn += insn->off; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 447 CONT_JMP; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 448 } \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 449 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 450 COND_JMP(u, JEQ, ==) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 451 COND_JMP(u, JNE, !=) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 452 COND_JMP(u, JGT, >) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 453 COND_JMP(u, JLT, <) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 454 COND_JMP(u, JGE, >=) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 455 COND_JMP(u, JLE, <=) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 456 COND_JMP(u, JSET, &) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 457 COND_JMP(s, JSGT, >) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 458 COND_JMP(s, JSLT, <) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 459 COND_JMP(s, JSGE, >=) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 460 COND_JMP(s, JSLE, <=) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 461 #undef COND_JMP 11087cf7f27f46 Ard Biesheuvel 2020-10-28 462 /* STX and ST and LDX*/ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 463 #define LDST(SIZEOP, SIZE) \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 464 STX_MEM_##SIZEOP: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 465 *(SIZE *)(unsigned long) (DST + insn->off) = SRC; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 466 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 467 ST_MEM_##SIZEOP: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 468 *(SIZE *)(unsigned long) (DST + insn->off) = IMM; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 469 CONT; \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 470 LDX_MEM_##SIZEOP: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 471 DST = *(SIZE *)(unsigned long) (SRC + insn->off); \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 472 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 473 11087cf7f27f46 Ard Biesheuvel 2020-10-28 474 LDST(B, u8) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 475 LDST(H, u16) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 476 LDST(W, u32) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 477 LDST(DW, u64) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 478 #undef LDST 11087cf7f27f46 Ard Biesheuvel 2020-10-28 479 #define LDX_PROBE(SIZEOP, SIZE) \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 480 LDX_PROBE_MEM_##SIZEOP: \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 481 bpf_probe_read_kernel(&DST, SIZE, (const void *)(long) (SRC + insn->off)); \ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 482 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 483 LDX_PROBE(B, 1) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 484 LDX_PROBE(H, 2) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 485 LDX_PROBE(W, 4) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 486 LDX_PROBE(DW, 8) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 487 #undef LDX_PROBE 11087cf7f27f46 Ard Biesheuvel 2020-10-28 488 11087cf7f27f46 Ard Biesheuvel 2020-10-28 489 STX_XADD_W: /* lock xadd *(u32 *)(dst_reg + off16) += src_reg */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 490 atomic_add((u32) SRC, (atomic_t *)(unsigned long) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 491 (DST + insn->off)); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 492 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 493 STX_XADD_DW: /* lock xadd *(u64 *)(dst_reg + off16) += src_reg */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 494 atomic64_add((u64) SRC, (atomic64_t *)(unsigned long) 11087cf7f27f46 Ard Biesheuvel 2020-10-28 495 (DST + insn->off)); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 496 CONT; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 497 11087cf7f27f46 Ard Biesheuvel 2020-10-28 498 default_label: 11087cf7f27f46 Ard Biesheuvel 2020-10-28 499 /* If we ever reach this, we have a bug somewhere. Die hard here 11087cf7f27f46 Ard Biesheuvel 2020-10-28 500 * instead of just returning 0; we could be somewhere in a subprog, 11087cf7f27f46 Ard Biesheuvel 2020-10-28 501 * so execution could continue otherwise which we do /not/ want. 11087cf7f27f46 Ard Biesheuvel 2020-10-28 502 * 11087cf7f27f46 Ard Biesheuvel 2020-10-28 503 * Note, verifier whitelists all opcodes in bpf_opcode_in_insntable(). 11087cf7f27f46 Ard Biesheuvel 2020-10-28 504 */ 11087cf7f27f46 Ard Biesheuvel 2020-10-28 505 pr_warn("BPF interpreter: unknown opcode %02x\n", insn->code); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 506 BUG_ON(1); 11087cf7f27f46 Ard Biesheuvel 2020-10-28 507 return 0; 11087cf7f27f46 Ard Biesheuvel 2020-10-28 508 } 11087cf7f27f46 Ard Biesheuvel 2020-10-28 509 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected]
.config.gz
Description: application/gzip
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