CC: [email protected] CC: Linux Memory Management List <[email protected]> TO: Miquel Raynal <[email protected]> CC: Alexandre Belloni <[email protected]>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: 52a0bcb60e40f30211cb5cbbb0f582ec4e91d896 commit: dd3c52846d5954acd43f0e771689302f27dadc28 [8313/11541] i3c: master: svc: Add Silvaco I3C master driver :::::: branch date: 11 hours ago :::::: commit date: 10 days ago config: x86_64-randconfig-m001-20210215 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> smatch warnings: drivers/i3c/master/svc-i3c-master.c:394 svc_i3c_master_ibi_work() error: uninitialized symbol 'dev'. drivers/i3c/master/svc-i3c-master.c:394 svc_i3c_master_ibi_work() error: we previously assumed 'dev' could be null (see line 372) drivers/i3c/master/svc-i3c-master.c:1021 svc_i3c_master_start_xfer_locked() error: uninitialized symbol 'ret'. vim +/dev +394 drivers/i3c/master/svc-i3c-master.c dd3c52846d5954 Miquel Raynal 2021-01-21 338 dd3c52846d5954 Miquel Raynal 2021-01-21 339 static void svc_i3c_master_ibi_work(struct work_struct *work) dd3c52846d5954 Miquel Raynal 2021-01-21 340 { dd3c52846d5954 Miquel Raynal 2021-01-21 341 struct svc_i3c_master *master = container_of(work, struct svc_i3c_master, ibi_work); dd3c52846d5954 Miquel Raynal 2021-01-21 342 struct svc_i3c_i2c_dev_data *data; dd3c52846d5954 Miquel Raynal 2021-01-21 343 unsigned int ibitype, ibiaddr; dd3c52846d5954 Miquel Raynal 2021-01-21 344 struct i3c_dev_desc *dev; dd3c52846d5954 Miquel Raynal 2021-01-21 345 u32 status, val; dd3c52846d5954 Miquel Raynal 2021-01-21 346 int ret; dd3c52846d5954 Miquel Raynal 2021-01-21 347 dd3c52846d5954 Miquel Raynal 2021-01-21 348 /* Acknowledge the incoming interrupt with the AUTOIBI mechanism */ dd3c52846d5954 Miquel Raynal 2021-01-21 349 writel(SVC_I3C_MCTRL_REQUEST_AUTO_IBI | dd3c52846d5954 Miquel Raynal 2021-01-21 350 SVC_I3C_MCTRL_IBIRESP_AUTO, dd3c52846d5954 Miquel Raynal 2021-01-21 351 master->regs + SVC_I3C_MCTRL); dd3c52846d5954 Miquel Raynal 2021-01-21 352 dd3c52846d5954 Miquel Raynal 2021-01-21 353 /* Wait for IBIWON, should take approximately 100us */ dd3c52846d5954 Miquel Raynal 2021-01-21 354 ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val, dd3c52846d5954 Miquel Raynal 2021-01-21 355 SVC_I3C_MSTATUS_IBIWON(val), 0, 1000); dd3c52846d5954 Miquel Raynal 2021-01-21 356 if (ret) { dd3c52846d5954 Miquel Raynal 2021-01-21 357 dev_err(master->dev, "Timeout when polling for IBIWON\n"); dd3c52846d5954 Miquel Raynal 2021-01-21 358 goto reenable_ibis; dd3c52846d5954 Miquel Raynal 2021-01-21 359 } dd3c52846d5954 Miquel Raynal 2021-01-21 360 dd3c52846d5954 Miquel Raynal 2021-01-21 361 /* Clear the interrupt status */ dd3c52846d5954 Miquel Raynal 2021-01-21 362 writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS); dd3c52846d5954 Miquel Raynal 2021-01-21 363 dd3c52846d5954 Miquel Raynal 2021-01-21 364 status = readl(master->regs + SVC_I3C_MSTATUS); dd3c52846d5954 Miquel Raynal 2021-01-21 365 ibitype = SVC_I3C_MSTATUS_IBITYPE(status); dd3c52846d5954 Miquel Raynal 2021-01-21 366 ibiaddr = SVC_I3C_MSTATUS_IBIADDR(status); dd3c52846d5954 Miquel Raynal 2021-01-21 367 dd3c52846d5954 Miquel Raynal 2021-01-21 368 /* Handle the critical responses to IBI's */ dd3c52846d5954 Miquel Raynal 2021-01-21 369 switch (ibitype) { dd3c52846d5954 Miquel Raynal 2021-01-21 370 case SVC_I3C_MSTATUS_IBITYPE_IBI: dd3c52846d5954 Miquel Raynal 2021-01-21 371 dev = svc_i3c_master_dev_from_addr(master, ibiaddr); dd3c52846d5954 Miquel Raynal 2021-01-21 @372 if (!dev) dd3c52846d5954 Miquel Raynal 2021-01-21 373 svc_i3c_master_nack_ibi(master); dd3c52846d5954 Miquel Raynal 2021-01-21 374 else dd3c52846d5954 Miquel Raynal 2021-01-21 375 svc_i3c_master_handle_ibi(master, dev); dd3c52846d5954 Miquel Raynal 2021-01-21 376 break; dd3c52846d5954 Miquel Raynal 2021-01-21 377 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: dd3c52846d5954 Miquel Raynal 2021-01-21 378 svc_i3c_master_ack_ibi(master, false); dd3c52846d5954 Miquel Raynal 2021-01-21 379 break; dd3c52846d5954 Miquel Raynal 2021-01-21 380 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: dd3c52846d5954 Miquel Raynal 2021-01-21 381 svc_i3c_master_nack_ibi(master); dd3c52846d5954 Miquel Raynal 2021-01-21 382 break; dd3c52846d5954 Miquel Raynal 2021-01-21 383 default: dd3c52846d5954 Miquel Raynal 2021-01-21 384 break; dd3c52846d5954 Miquel Raynal 2021-01-21 385 } dd3c52846d5954 Miquel Raynal 2021-01-21 386 dd3c52846d5954 Miquel Raynal 2021-01-21 387 /* dd3c52846d5954 Miquel Raynal 2021-01-21 388 * If an error happened, we probably got interrupted and the exchange dd3c52846d5954 Miquel Raynal 2021-01-21 389 * timedout. In this case we just drop everything, emit a stop and wait dd3c52846d5954 Miquel Raynal 2021-01-21 390 * for the slave to interrupt again. dd3c52846d5954 Miquel Raynal 2021-01-21 391 */ dd3c52846d5954 Miquel Raynal 2021-01-21 392 if (svc_i3c_master_error(master)) { dd3c52846d5954 Miquel Raynal 2021-01-21 393 if (master->ibi.tbq_slot) { dd3c52846d5954 Miquel Raynal 2021-01-21 @394 data = i3c_dev_get_master_data(dev); dd3c52846d5954 Miquel Raynal 2021-01-21 395 i3c_generic_ibi_recycle_slot(data->ibi_pool, dd3c52846d5954 Miquel Raynal 2021-01-21 396 master->ibi.tbq_slot); dd3c52846d5954 Miquel Raynal 2021-01-21 397 master->ibi.tbq_slot = NULL; dd3c52846d5954 Miquel Raynal 2021-01-21 398 } dd3c52846d5954 Miquel Raynal 2021-01-21 399 dd3c52846d5954 Miquel Raynal 2021-01-21 400 svc_i3c_master_emit_stop(master); dd3c52846d5954 Miquel Raynal 2021-01-21 401 dd3c52846d5954 Miquel Raynal 2021-01-21 402 goto reenable_ibis; dd3c52846d5954 Miquel Raynal 2021-01-21 403 } dd3c52846d5954 Miquel Raynal 2021-01-21 404 dd3c52846d5954 Miquel Raynal 2021-01-21 405 /* Handle the non critical tasks */ dd3c52846d5954 Miquel Raynal 2021-01-21 406 switch (ibitype) { dd3c52846d5954 Miquel Raynal 2021-01-21 407 case SVC_I3C_MSTATUS_IBITYPE_IBI: dd3c52846d5954 Miquel Raynal 2021-01-21 408 if (dev) { dd3c52846d5954 Miquel Raynal 2021-01-21 409 i3c_master_queue_ibi(dev, master->ibi.tbq_slot); dd3c52846d5954 Miquel Raynal 2021-01-21 410 master->ibi.tbq_slot = NULL; dd3c52846d5954 Miquel Raynal 2021-01-21 411 } dd3c52846d5954 Miquel Raynal 2021-01-21 412 svc_i3c_master_emit_stop(master); dd3c52846d5954 Miquel Raynal 2021-01-21 413 break; dd3c52846d5954 Miquel Raynal 2021-01-21 414 case SVC_I3C_MSTATUS_IBITYPE_HOT_JOIN: dd3c52846d5954 Miquel Raynal 2021-01-21 415 queue_work(master->base.wq, &master->hj_work); dd3c52846d5954 Miquel Raynal 2021-01-21 416 break; dd3c52846d5954 Miquel Raynal 2021-01-21 417 case SVC_I3C_MSTATUS_IBITYPE_MASTER_REQUEST: dd3c52846d5954 Miquel Raynal 2021-01-21 418 default: dd3c52846d5954 Miquel Raynal 2021-01-21 419 break; dd3c52846d5954 Miquel Raynal 2021-01-21 420 } dd3c52846d5954 Miquel Raynal 2021-01-21 421 dd3c52846d5954 Miquel Raynal 2021-01-21 422 reenable_ibis: dd3c52846d5954 Miquel Raynal 2021-01-21 423 svc_i3c_master_enable_interrupts(master, SVC_I3C_MINT_SLVSTART); dd3c52846d5954 Miquel Raynal 2021-01-21 424 } dd3c52846d5954 Miquel Raynal 2021-01-21 425 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected]
.config.gz
Description: application/gzip
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