CC: [email protected] BCC: [email protected] CC: Alison Schofield <[email protected]> CC: Vishal Verma <[email protected]> CC: Ira Weiny <[email protected]> CC: Ben Widawsky <[email protected]> CC: Dan Williams <[email protected]> CC: [email protected] TO: Ben Widawsky <[email protected]> CC: Dan Williams <[email protected]>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git preview head: 9b688fc651b9d2b633e8d959454670aba1c39162 commit: 2ecd98fe1cb0746e61b6543d93939d87519e2df9 [62/78] cxl/region: Add support for single switch level :::::: branch date: 25 hours ago :::::: commit date: 9 days ago config: alpha-randconfig-c004-20220227 (https://download.01.org/0day-ci/archive/20220227/[email protected]/config) compiler: alpha-linux-gcc (GCC) 11.2.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Julia Lawall <[email protected]> cocci warnings: (new ones prefixed by >>) >> drivers/cxl/region.c:550:5-16: ERROR: invalid reference to the index >> variable of the iterator on line 543 vim +550 drivers/cxl/region.c b15cb12c2369e0 Ben Widawsky 2022-02-11 413 786e9e58377374 Ben Widawsky 2022-02-11 414 /** 786e9e58377374 Ben Widawsky 2022-02-11 415 * region_hb_rp_config_valid() - determine root port ordering is correct 786e9e58377374 Ben Widawsky 2022-02-11 416 * @cxlr: Region to validate 786e9e58377374 Ben Widawsky 2022-02-11 417 * @rootd: root decoder for this @cxlr b15cb12c2369e0 Ben Widawsky 2022-02-11 418 * @state_update: Whether or not to update port state 786e9e58377374 Ben Widawsky 2022-02-11 419 * 786e9e58377374 Ben Widawsky 2022-02-11 420 * The algorithm is outlined in 2.13.15 "Verify HB root port configuration 786e9e58377374 Ben Widawsky 2022-02-11 421 * sequence" of the CXL Memory Device SW Guide (Rev1p0). 786e9e58377374 Ben Widawsky 2022-02-11 422 * 786e9e58377374 Ben Widawsky 2022-02-11 423 * Returns true if the configuration is valid. 786e9e58377374 Ben Widawsky 2022-02-11 424 */ b15cb12c2369e0 Ben Widawsky 2022-02-11 425 static bool region_hb_rp_config_valid(struct cxl_region *cxlr, b15cb12c2369e0 Ben Widawsky 2022-02-11 426 const struct cxl_decoder *rootd, b15cb12c2369e0 Ben Widawsky 2022-02-11 427 bool state_update) 786e9e58377374 Ben Widawsky 2022-02-11 428 { 2ecd98fe1cb074 Ben Widawsky 2022-02-11 429 const int region_ig = cxl_to_ig(cxlr->config.interleave_granularity); 2ecd98fe1cb074 Ben Widawsky 2022-02-11 430 const int region_eniw = cxl_to_eniw(cxlr->config.interleave_ways); 8ed598d187016c Ben Widawsky 2022-02-11 431 const int num_root_ports = get_num_root_ports(cxlr); 8ed598d187016c Ben Widawsky 2022-02-11 432 struct cxl_port *hbs[CXL_DECODER_MAX_INTERLEAVE]; b15cb12c2369e0 Ben Widawsky 2022-02-11 433 struct cxl_decoder *cxld, *c; 8ed598d187016c Ben Widawsky 2022-02-11 434 int hb_count, i; 8ed598d187016c Ben Widawsky 2022-02-11 435 8ed598d187016c Ben Widawsky 2022-02-11 436 hb_count = get_unique_hostbridges(cxlr, hbs); 8ed598d187016c Ben Widawsky 2022-02-11 437 2ecd98fe1cb074 Ben Widawsky 2022-02-11 438 /* TODO: support multiple levels of switches */ 2ecd98fe1cb074 Ben Widawsky 2022-02-11 439 if (has_multi_switch(cxlr)) 2ecd98fe1cb074 Ben Widawsky 2022-02-11 440 return false; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 441 2ecd98fe1cb074 Ben Widawsky 2022-02-11 442 /* TODO: x3 interleave for switches is hard. */ 2ecd98fe1cb074 Ben Widawsky 2022-02-11 443 if (has_switch(cxlr) && !is_power_of_2(region_ways(cxlr))) 8ed598d187016c Ben Widawsky 2022-02-11 444 return false; 8ed598d187016c Ben Widawsky 2022-02-11 445 8ed598d187016c Ben Widawsky 2022-02-11 446 /* 8ed598d187016c Ben Widawsky 2022-02-11 447 * Are all devices in this region on the same CXL Host Bridge 8ed598d187016c Ben Widawsky 2022-02-11 448 * Root Port? 8ed598d187016c Ben Widawsky 2022-02-11 449 */ b15cb12c2369e0 Ben Widawsky 2022-02-11 450 if (num_root_ports == 1 && !has_switch(cxlr) && state_update) b15cb12c2369e0 Ben Widawsky 2022-02-11 451 return simple_config(cxlr, hbs[0]); 8ed598d187016c Ben Widawsky 2022-02-11 452 8ed598d187016c Ben Widawsky 2022-02-11 453 for (i = 0; i < hb_count; i++) { a87877add7dded Ben Widawsky 2022-02-11 454 struct cxl_decoder *cxld; 8ed598d187016c Ben Widawsky 2022-02-11 455 int idx, position_mask; 8ed598d187016c Ben Widawsky 2022-02-11 456 struct cxl_dport *rp; 8ed598d187016c Ben Widawsky 2022-02-11 457 struct cxl_port *hb; 8ed598d187016c Ben Widawsky 2022-02-11 458 8ed598d187016c Ben Widawsky 2022-02-11 459 /* Get next CXL Host Bridge this region spans */ 8ed598d187016c Ben Widawsky 2022-02-11 460 hb = hbs[i]; 8ed598d187016c Ben Widawsky 2022-02-11 461 b15cb12c2369e0 Ben Widawsky 2022-02-11 462 if (state_update) { b15cb12c2369e0 Ben Widawsky 2022-02-11 463 cxld = get_decoder(cxlr, hb); b15cb12c2369e0 Ben Widawsky 2022-02-11 464 if (IS_ERR(cxld)) { b15cb12c2369e0 Ben Widawsky 2022-02-11 465 dev_dbg(&cxlr->dev, b15cb12c2369e0 Ben Widawsky 2022-02-11 466 "Couldn't get decoder for %s\n", b15cb12c2369e0 Ben Widawsky 2022-02-11 467 dev_name(&hb->dev)); b15cb12c2369e0 Ben Widawsky 2022-02-11 468 goto err; b15cb12c2369e0 Ben Widawsky 2022-02-11 469 } b15cb12c2369e0 Ben Widawsky 2022-02-11 470 cxld->interleave_ways = 0; b15cb12c2369e0 Ben Widawsky 2022-02-11 471 cxld->interleave_granularity = region_granularity(cxlr); b15cb12c2369e0 Ben Widawsky 2022-02-11 472 } else { b15cb12c2369e0 Ben Widawsky 2022-02-11 473 cxld = NULL; b15cb12c2369e0 Ben Widawsky 2022-02-11 474 } b15cb12c2369e0 Ben Widawsky 2022-02-11 475 8ed598d187016c Ben Widawsky 2022-02-11 476 /* 8ed598d187016c Ben Widawsky 2022-02-11 477 * Calculate the position mask: NumRootPorts = 2^PositionMask 8ed598d187016c Ben Widawsky 2022-02-11 478 * for this region. 8ed598d187016c Ben Widawsky 2022-02-11 479 * 8ed598d187016c Ben Widawsky 2022-02-11 480 * XXX: pos_mask is actually (1 << PositionMask) - 1 8ed598d187016c Ben Widawsky 2022-02-11 481 */ 8ed598d187016c Ben Widawsky 2022-02-11 482 position_mask = (1 << (ilog2(num_root_ports))) - 1; 8ed598d187016c Ben Widawsky 2022-02-11 483 8ed598d187016c Ben Widawsky 2022-02-11 484 /* 8ed598d187016c Ben Widawsky 2022-02-11 485 * Calculate the PortGrouping for each device on this CXL Host 8ed598d187016c Ben Widawsky 2022-02-11 486 * Bridge Root Port: 8ed598d187016c Ben Widawsky 2022-02-11 487 * PortGrouping = RegionLabel.Position & PositionMask 8ed598d187016c Ben Widawsky 2022-02-11 488 * 8ed598d187016c Ben Widawsky 2022-02-11 489 * The following nest iterators effectively iterate over each 8ed598d187016c Ben Widawsky 2022-02-11 490 * root port in the region. 8ed598d187016c Ben Widawsky 2022-02-11 491 * for_each_unique_rootport(rp, cxlr) 8ed598d187016c Ben Widawsky 2022-02-11 492 */ 8ed598d187016c Ben Widawsky 2022-02-11 493 list_for_each_entry(rp, &hb->dports, list) { 8ed598d187016c Ben Widawsky 2022-02-11 494 struct cxl_memdev *ep; 8ed598d187016c Ben Widawsky 2022-02-11 495 int port_grouping = -1; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 496 int target_ndx; 8ed598d187016c Ben Widawsky 2022-02-11 497 8ed598d187016c Ben Widawsky 2022-02-11 498 for_each_cxl_endpoint_hb(ep, cxlr, hb, idx) { 2ecd98fe1cb074 Ben Widawsky 2022-02-11 499 struct cxl_decoder *switch_cxld; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 500 struct cxl_dport *target; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 501 struct cxl_port *switch_port; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 502 bool found = false; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 503 8ed598d187016c Ben Widawsky 2022-02-11 504 if (get_rp(ep) != rp) 8ed598d187016c Ben Widawsky 2022-02-11 505 continue; 8ed598d187016c Ben Widawsky 2022-02-11 506 8ed598d187016c Ben Widawsky 2022-02-11 507 if (port_grouping == -1) 8ed598d187016c Ben Widawsky 2022-02-11 508 port_grouping = idx & position_mask; 8ed598d187016c Ben Widawsky 2022-02-11 509 8ed598d187016c Ben Widawsky 2022-02-11 510 /* 8ed598d187016c Ben Widawsky 2022-02-11 511 * Do all devices in the region connected to this CXL 8ed598d187016c Ben Widawsky 2022-02-11 512 * Host Bridge Root Port have the same PortGrouping? 8ed598d187016c Ben Widawsky 2022-02-11 513 */ 8ed598d187016c Ben Widawsky 2022-02-11 514 if ((idx & position_mask) != port_grouping) { 8ed598d187016c Ben Widawsky 2022-02-11 515 dev_dbg(&cxlr->dev, 8ed598d187016c Ben Widawsky 2022-02-11 516 "One or more devices are not connected to the correct Host Bridge Root Port\n"); b15cb12c2369e0 Ben Widawsky 2022-02-11 517 goto err; 8ed598d187016c Ben Widawsky 2022-02-11 518 } a87877add7dded Ben Widawsky 2022-02-11 519 a87877add7dded Ben Widawsky 2022-02-11 520 if (!state_update) a87877add7dded Ben Widawsky 2022-02-11 521 continue; a87877add7dded Ben Widawsky 2022-02-11 522 a87877add7dded Ben Widawsky 2022-02-11 523 if (dev_WARN_ONCE(&cxld->dev, a87877add7dded Ben Widawsky 2022-02-11 524 port_grouping >= cxld->nr_targets, a87877add7dded Ben Widawsky 2022-02-11 525 "Invalid port grouping %d/%d\n", a87877add7dded Ben Widawsky 2022-02-11 526 port_grouping, cxld->nr_targets)) a87877add7dded Ben Widawsky 2022-02-11 527 goto err; a87877add7dded Ben Widawsky 2022-02-11 528 a87877add7dded Ben Widawsky 2022-02-11 529 cxld->interleave_ways++; a87877add7dded Ben Widawsky 2022-02-11 530 cxld->target[port_grouping] = get_rp(ep); 2ecd98fe1cb074 Ben Widawsky 2022-02-11 531 2ecd98fe1cb074 Ben Widawsky 2022-02-11 532 /* 2ecd98fe1cb074 Ben Widawsky 2022-02-11 533 * At least one switch is connected here if the endpoint 2ecd98fe1cb074 Ben Widawsky 2022-02-11 534 * has a depth > 2 2ecd98fe1cb074 Ben Widawsky 2022-02-11 535 */ 2ecd98fe1cb074 Ben Widawsky 2022-02-11 536 if (ep->port->depth == 2) 2ecd98fe1cb074 Ben Widawsky 2022-02-11 537 continue; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 538 2ecd98fe1cb074 Ben Widawsky 2022-02-11 539 /* Check the staged list to see if this 2ecd98fe1cb074 Ben Widawsky 2022-02-11 540 * port has already been added 2ecd98fe1cb074 Ben Widawsky 2022-02-11 541 */ 2ecd98fe1cb074 Ben Widawsky 2022-02-11 542 switch_port = get_switch(ep); 2ecd98fe1cb074 Ben Widawsky 2022-02-11 @543 list_for_each_entry(switch_cxld, &cxlr->staged_list, region_link) { 2ecd98fe1cb074 Ben Widawsky 2022-02-11 544 if (to_cxl_port(switch_cxld->dev.parent) == switch_port) 2ecd98fe1cb074 Ben Widawsky 2022-02-11 545 found = true; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 546 } 2ecd98fe1cb074 Ben Widawsky 2022-02-11 547 2ecd98fe1cb074 Ben Widawsky 2022-02-11 548 if (found) { 2ecd98fe1cb074 Ben Widawsky 2022-02-11 549 target = cxl_find_dport_by_dev(switch_port, ep->dev.parent->parent); 2ecd98fe1cb074 Ben Widawsky 2022-02-11 @550 switch_cxld->target[target_ndx++] = target; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 551 continue; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 552 } 2ecd98fe1cb074 Ben Widawsky 2022-02-11 553 2ecd98fe1cb074 Ben Widawsky 2022-02-11 554 target_ndx = 0; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 555 2ecd98fe1cb074 Ben Widawsky 2022-02-11 556 switch_cxld = get_decoder(cxlr, switch_port); 2ecd98fe1cb074 Ben Widawsky 2022-02-11 557 switch_cxld->interleave_ways++; 2ecd98fe1cb074 Ben Widawsky 2022-02-11 558 switch_cxld->interleave_granularity = cxl_to_ways(region_ig + region_eniw); 8ed598d187016c Ben Widawsky 2022-02-11 559 } 8ed598d187016c Ben Widawsky 2022-02-11 560 } 8ed598d187016c Ben Widawsky 2022-02-11 561 } 8ed598d187016c Ben Widawsky 2022-02-11 562 786e9e58377374 Ben Widawsky 2022-02-11 563 return true; b15cb12c2369e0 Ben Widawsky 2022-02-11 564 b15cb12c2369e0 Ben Widawsky 2022-02-11 565 err: b15cb12c2369e0 Ben Widawsky 2022-02-11 566 dev_dbg(&cxlr->dev, "Couldn't get decoder for region\n"); b15cb12c2369e0 Ben Widawsky 2022-02-11 567 list_for_each_entry_safe(cxld, c, &cxlr->staged_list, region_link) b15cb12c2369e0 Ben Widawsky 2022-02-11 568 cxl_put_decoder(cxld); b15cb12c2369e0 Ben Widawsky 2022-02-11 569 b15cb12c2369e0 Ben Widawsky 2022-02-11 570 return false; 786e9e58377374 Ben Widawsky 2022-02-11 571 } 786e9e58377374 Ben Widawsky 2022-02-11 572 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/[email protected] _______________________________________________ kbuild mailing list -- [email protected] To unsubscribe send an email to [email protected]
