CC: [email protected] BCC: [email protected] In-Reply-To: <[email protected]> References: <[email protected]> TO: "Maciej W. Rozycki" <[email protected]> TO: "Greg Kroah-Hartman" <[email protected]> TO: Jiri Slaby <[email protected]> CC: Andy Shevchenko <[email protected]> CC: [email protected] CC: [email protected]
Hi "Maciej, I love your patch! Perhaps something to improve: [auto build test WARNING on tty/tty-testing] [also build test WARNING on usb/usb-testing linus/master v5.18-rc3 next-20220414] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch] url: https://github.com/intel-lab-lkp/linux/commits/Maciej-W-Rozycki/serial-8250-Fixes-for-Oxford-Semiconductor-950-UARTs/20220418-234958 base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing :::::: branch date: 12 hours ago :::::: commit date: 12 hours ago config: i386-randconfig-m021-20220418 (https://download.01.org/0day-ci/archive/20220419/[email protected]/config) compiler: gcc-11 (Debian 11.2.0-19) 11.2.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> New smatch warnings: drivers/tty/serial/8250/8250_pci.c:1175 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'tcr'. drivers/tty/serial/8250/8250_pci.c:1176 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. drivers/tty/serial/8250/8250_pci.c:1184 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. Old smatch warnings: drivers/tty/serial/8250/8250_pci.c:1180 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'quot'. drivers/tty/serial/8250/8250_pci.c:1194 pci_oxsemi_tornado_get_divisor() error: uninitialized symbol 'cpr'. vim +/tcr +1175 drivers/tty/serial/8250/8250_pci.c 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1053 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1054 /* 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1055 * Determine the oversampling rate, the clock prescaler, and the clock 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1056 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1057 * which is four times the baud base, and the prescaler increments in 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1058 * steps of 1/8. Therefore to make calculations on integers we need 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1059 * to use a scaled clock rate, which is the baud base multiplied by 32 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1060 * (or our assumed UART clock rate multiplied by 2). 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1061 * 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1062 * The allowed oversampling rates are from 4 up to 16 inclusive (values 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1063 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1064 * values between 1.000 and 63.875 inclusive (operation for values from 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1065 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1066 * unsigned 16-bit integer. 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1067 * 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1068 * For the most accurate baud rate we use a table of predetermined 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1069 * oversampling rates and clock prescalers that records all possible 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1070 * products of the two parameters in the range from 4 up to 255 inclusive, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1071 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1072 * by 8. The table is sorted by the decreasing value of the oversampling 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1073 * rate and ties are resolved by sorting by the decreasing value of the 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1074 * product. This way preference is given to higher oversampling rates. 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1075 * 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1076 * We iterate over the table and choose the product of an oversampling 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1077 * rate and a clock prescaler that gives the lowest integer division 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1078 * result deviation, or if an exact integer divider is found we stop 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1079 * looking for it right away. We do some fixup if the resulting clock 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1080 * divisor required would be out of its unsigned 16-bit integer range. 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1081 * 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1082 * Finally we abuse the supposed fractional part returned to encode the 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1083 * 4-bit value of the oversampling rate and the 9-bit value of the clock 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1084 * prescaler which will end up in the TCR and CPR/CPR2 registers. 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1085 */ 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1086 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1087 unsigned int baud, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1088 unsigned int *frac) 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1089 { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1090 static u8 p[][2] = { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1091 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1092 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1093 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1094 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1095 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1096 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1097 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1098 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1099 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1100 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1101 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1102 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1103 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1104 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1105 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1106 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1107 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1108 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1109 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1110 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1111 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1112 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1113 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1114 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1115 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1116 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1117 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1118 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1119 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1120 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1121 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1122 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1123 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1124 { 4, 9, }, { 4, 8, }, 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1125 }; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1126 /* Scale the quotient for comparison to get the fractional part. */ 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1127 const unsigned int quot_scale = 65536; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1128 unsigned int sclk = port->uartclk * 2; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1129 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1130 unsigned int best_squot; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1131 unsigned int squot; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1132 unsigned int quot; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1133 u16 cpr; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1134 u8 tcr; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1135 int i; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1136 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1137 /* Old custom speed handling. */ 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1138 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1139 unsigned int cust_div = port->custom_divisor; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1140 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1141 quot = cust_div & UART_DIV_MAX; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1142 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1143 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1144 if (cpr < OXSEMI_TORNADO_CPR_MIN) 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1145 cpr = OXSEMI_TORNADO_CPR_DEF; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1146 } else { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1147 best_squot = quot_scale; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1148 for (i = 0; i < ARRAY_SIZE(p); i++) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1149 unsigned int spre; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1150 unsigned int srem; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1151 u8 cp; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1152 u8 tc; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1153 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1154 tc = p[i][0]; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1155 cp = p[i][1]; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1156 spre = tc * cp; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1157 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1158 srem = sdiv % spre; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1159 if (srem > spre / 2) 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1160 srem = spre - srem; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1161 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1162 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1163 if (srem == 0) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1164 tcr = tc; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1165 cpr = cp; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1166 quot = sdiv / spre; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1167 break; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1168 } else if (squot < best_squot) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1169 best_squot = squot; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1170 tcr = tc; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1171 cpr = cp; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1172 quot = DIV_ROUND_CLOSEST(sdiv, spre); 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1173 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1174 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 @1175 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 @1176 quot % 2 == 0) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1177 quot >>= 1; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1178 tcr <<= 1; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1179 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1180 while (quot > UART_DIV_MAX) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1181 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1182 quot >>= 1; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1183 tcr <<= 1; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 @1184 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1185 quot >>= 1; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1186 cpr <<= 1; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1187 } else { 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1188 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1189 cpr = OXSEMI_TORNADO_CPR_MASK; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1190 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1191 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1192 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1193 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1194 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1195 return quot; 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1196 } 42c36d19c0b2a9 Maciej W. Rozycki 2022-04-18 1197 -- 0-DAY CI Kernel Test Service https://01.org/lkp _______________________________________________ kbuild mailing list -- [email protected] To unsubscribe send an email to [email protected]
