CC: [email protected] BCC: [email protected] CC: Alison Schofield <[email protected]> CC: Vishal Verma <[email protected]> CC: Ira Weiny <[email protected]> CC: Ben Widawsky <[email protected]> CC: Dan Williams <[email protected]> CC: [email protected] TO: Ben Widawsky <[email protected]> CC: Dan Williams <[email protected]>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git preview head: 9c642abd8b31d895f34186bd72b7360083b58492 commit: 50b9ca060c8e4827a3871b94d983040eac80fac8 [63/67] cxl/region: Add support for single switch level :::::: branch date: 7 hours ago :::::: commit date: 7 hours ago config: x86_64-randconfig-c002-20220509 (https://download.01.org/0day-ci/archive/20220512/[email protected]/config) compiler: gcc-11 (Debian 11.2.0-20) 11.2.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <[email protected]> Reported-by: Julia Lawall <[email protected]> cocci warnings: (new ones prefixed by >>) >> drivers/cxl/region.c:550:5-16: ERROR: invalid reference to the index >> variable of the iterator on line 543 vim +550 drivers/cxl/region.c 5c4ecc7471fee0 Ben Widawsky 2022-02-11 413 e3a336d0e7c1ec Ben Widawsky 2022-02-11 414 /** e3a336d0e7c1ec Ben Widawsky 2022-02-11 415 * region_hb_rp_config_valid() - determine root port ordering is correct e3a336d0e7c1ec Ben Widawsky 2022-02-11 416 * @cxlr: Region to validate e3a336d0e7c1ec Ben Widawsky 2022-02-11 417 * @rootd: root decoder for this @cxlr 5c4ecc7471fee0 Ben Widawsky 2022-02-11 418 * @state_update: Whether or not to update port state e3a336d0e7c1ec Ben Widawsky 2022-02-11 419 * e3a336d0e7c1ec Ben Widawsky 2022-02-11 420 * The algorithm is outlined in 2.13.15 "Verify HB root port configuration e3a336d0e7c1ec Ben Widawsky 2022-02-11 421 * sequence" of the CXL Memory Device SW Guide (Rev1p0). e3a336d0e7c1ec Ben Widawsky 2022-02-11 422 * e3a336d0e7c1ec Ben Widawsky 2022-02-11 423 * Returns true if the configuration is valid. e3a336d0e7c1ec Ben Widawsky 2022-02-11 424 */ 5c4ecc7471fee0 Ben Widawsky 2022-02-11 425 static bool region_hb_rp_config_valid(struct cxl_region *cxlr, 5c4ecc7471fee0 Ben Widawsky 2022-02-11 426 const struct cxl_decoder *rootd, 5c4ecc7471fee0 Ben Widawsky 2022-02-11 427 bool state_update) e3a336d0e7c1ec Ben Widawsky 2022-02-11 428 { 50b9ca060c8e48 Ben Widawsky 2022-02-11 429 const int region_ig = cxl_to_ig(cxlr->config.interleave_granularity); 50b9ca060c8e48 Ben Widawsky 2022-02-11 430 const int region_eniw = cxl_to_eniw(cxlr->config.interleave_ways); 00b0519c6f9af5 Ben Widawsky 2022-02-11 431 const int num_root_ports = get_num_root_ports(cxlr); 00b0519c6f9af5 Ben Widawsky 2022-02-11 432 struct cxl_port *hbs[CXL_DECODER_MAX_INTERLEAVE]; 5c4ecc7471fee0 Ben Widawsky 2022-02-11 433 struct cxl_decoder *cxld, *c; 00b0519c6f9af5 Ben Widawsky 2022-02-11 434 int hb_count, i; 00b0519c6f9af5 Ben Widawsky 2022-02-11 435 00b0519c6f9af5 Ben Widawsky 2022-02-11 436 hb_count = get_unique_hostbridges(cxlr, hbs); 00b0519c6f9af5 Ben Widawsky 2022-02-11 437 50b9ca060c8e48 Ben Widawsky 2022-02-11 438 /* TODO: support multiple levels of switches */ 50b9ca060c8e48 Ben Widawsky 2022-02-11 439 if (has_multi_switch(cxlr)) 50b9ca060c8e48 Ben Widawsky 2022-02-11 440 return false; 50b9ca060c8e48 Ben Widawsky 2022-02-11 441 50b9ca060c8e48 Ben Widawsky 2022-02-11 442 /* TODO: x3 interleave for switches is hard. */ 50b9ca060c8e48 Ben Widawsky 2022-02-11 443 if (has_switch(cxlr) && !is_power_of_2(region_ways(cxlr))) 00b0519c6f9af5 Ben Widawsky 2022-02-11 444 return false; 00b0519c6f9af5 Ben Widawsky 2022-02-11 445 00b0519c6f9af5 Ben Widawsky 2022-02-11 446 /* 00b0519c6f9af5 Ben Widawsky 2022-02-11 447 * Are all devices in this region on the same CXL Host Bridge 00b0519c6f9af5 Ben Widawsky 2022-02-11 448 * Root Port? 00b0519c6f9af5 Ben Widawsky 2022-02-11 449 */ 5c4ecc7471fee0 Ben Widawsky 2022-02-11 450 if (num_root_ports == 1 && !has_switch(cxlr) && state_update) 5c4ecc7471fee0 Ben Widawsky 2022-02-11 451 return simple_config(cxlr, hbs[0]); 00b0519c6f9af5 Ben Widawsky 2022-02-11 452 00b0519c6f9af5 Ben Widawsky 2022-02-11 453 for (i = 0; i < hb_count; i++) { 0184ca5ccb0827 Ben Widawsky 2022-02-11 454 struct cxl_decoder *cxld; 00b0519c6f9af5 Ben Widawsky 2022-02-11 455 int idx, position_mask; 00b0519c6f9af5 Ben Widawsky 2022-02-11 456 struct cxl_dport *rp; 00b0519c6f9af5 Ben Widawsky 2022-02-11 457 struct cxl_port *hb; 00b0519c6f9af5 Ben Widawsky 2022-02-11 458 00b0519c6f9af5 Ben Widawsky 2022-02-11 459 /* Get next CXL Host Bridge this region spans */ 00b0519c6f9af5 Ben Widawsky 2022-02-11 460 hb = hbs[i]; 00b0519c6f9af5 Ben Widawsky 2022-02-11 461 5c4ecc7471fee0 Ben Widawsky 2022-02-11 462 if (state_update) { 5c4ecc7471fee0 Ben Widawsky 2022-02-11 463 cxld = get_decoder(cxlr, hb); 5c4ecc7471fee0 Ben Widawsky 2022-02-11 464 if (IS_ERR(cxld)) { 5c4ecc7471fee0 Ben Widawsky 2022-02-11 465 dev_dbg(&cxlr->dev, 5c4ecc7471fee0 Ben Widawsky 2022-02-11 466 "Couldn't get decoder for %s\n", 5c4ecc7471fee0 Ben Widawsky 2022-02-11 467 dev_name(&hb->dev)); 5c4ecc7471fee0 Ben Widawsky 2022-02-11 468 goto err; 5c4ecc7471fee0 Ben Widawsky 2022-02-11 469 } 5c4ecc7471fee0 Ben Widawsky 2022-02-11 470 cxld->interleave_ways = 0; 5c4ecc7471fee0 Ben Widawsky 2022-02-11 471 cxld->interleave_granularity = region_granularity(cxlr); 5c4ecc7471fee0 Ben Widawsky 2022-02-11 472 } else { 5c4ecc7471fee0 Ben Widawsky 2022-02-11 473 cxld = NULL; 5c4ecc7471fee0 Ben Widawsky 2022-02-11 474 } 5c4ecc7471fee0 Ben Widawsky 2022-02-11 475 00b0519c6f9af5 Ben Widawsky 2022-02-11 476 /* 00b0519c6f9af5 Ben Widawsky 2022-02-11 477 * Calculate the position mask: NumRootPorts = 2^PositionMask 00b0519c6f9af5 Ben Widawsky 2022-02-11 478 * for this region. 00b0519c6f9af5 Ben Widawsky 2022-02-11 479 * 00b0519c6f9af5 Ben Widawsky 2022-02-11 480 * XXX: pos_mask is actually (1 << PositionMask) - 1 00b0519c6f9af5 Ben Widawsky 2022-02-11 481 */ 00b0519c6f9af5 Ben Widawsky 2022-02-11 482 position_mask = (1 << (ilog2(num_root_ports))) - 1; 00b0519c6f9af5 Ben Widawsky 2022-02-11 483 00b0519c6f9af5 Ben Widawsky 2022-02-11 484 /* 00b0519c6f9af5 Ben Widawsky 2022-02-11 485 * Calculate the PortGrouping for each device on this CXL Host 00b0519c6f9af5 Ben Widawsky 2022-02-11 486 * Bridge Root Port: 00b0519c6f9af5 Ben Widawsky 2022-02-11 487 * PortGrouping = RegionLabel.Position & PositionMask 00b0519c6f9af5 Ben Widawsky 2022-02-11 488 * 00b0519c6f9af5 Ben Widawsky 2022-02-11 489 * The following nest iterators effectively iterate over each 00b0519c6f9af5 Ben Widawsky 2022-02-11 490 * root port in the region. 00b0519c6f9af5 Ben Widawsky 2022-02-11 491 * for_each_unique_rootport(rp, cxlr) 00b0519c6f9af5 Ben Widawsky 2022-02-11 492 */ 00b0519c6f9af5 Ben Widawsky 2022-02-11 493 list_for_each_entry(rp, &hb->dports, list) { 00b0519c6f9af5 Ben Widawsky 2022-02-11 494 struct cxl_memdev *ep; 00b0519c6f9af5 Ben Widawsky 2022-02-11 495 int port_grouping = -1; 50b9ca060c8e48 Ben Widawsky 2022-02-11 496 int target_ndx; 00b0519c6f9af5 Ben Widawsky 2022-02-11 497 00b0519c6f9af5 Ben Widawsky 2022-02-11 498 for_each_cxl_endpoint_hb(ep, cxlr, hb, idx) { 50b9ca060c8e48 Ben Widawsky 2022-02-11 499 struct cxl_decoder *switch_cxld; 50b9ca060c8e48 Ben Widawsky 2022-02-11 500 struct cxl_dport *target; 50b9ca060c8e48 Ben Widawsky 2022-02-11 501 struct cxl_port *switch_port; 50b9ca060c8e48 Ben Widawsky 2022-02-11 502 bool found = false; 50b9ca060c8e48 Ben Widawsky 2022-02-11 503 00b0519c6f9af5 Ben Widawsky 2022-02-11 504 if (get_rp(ep) != rp) 00b0519c6f9af5 Ben Widawsky 2022-02-11 505 continue; 00b0519c6f9af5 Ben Widawsky 2022-02-11 506 00b0519c6f9af5 Ben Widawsky 2022-02-11 507 if (port_grouping == -1) 00b0519c6f9af5 Ben Widawsky 2022-02-11 508 port_grouping = idx & position_mask; 00b0519c6f9af5 Ben Widawsky 2022-02-11 509 00b0519c6f9af5 Ben Widawsky 2022-02-11 510 /* 00b0519c6f9af5 Ben Widawsky 2022-02-11 511 * Do all devices in the region connected to this CXL 00b0519c6f9af5 Ben Widawsky 2022-02-11 512 * Host Bridge Root Port have the same PortGrouping? 00b0519c6f9af5 Ben Widawsky 2022-02-11 513 */ 00b0519c6f9af5 Ben Widawsky 2022-02-11 514 if ((idx & position_mask) != port_grouping) { 00b0519c6f9af5 Ben Widawsky 2022-02-11 515 dev_dbg(&cxlr->dev, 00b0519c6f9af5 Ben Widawsky 2022-02-11 516 "One or more devices are not connected to the correct Host Bridge Root Port\n"); 5c4ecc7471fee0 Ben Widawsky 2022-02-11 517 goto err; 00b0519c6f9af5 Ben Widawsky 2022-02-11 518 } 0184ca5ccb0827 Ben Widawsky 2022-02-11 519 0184ca5ccb0827 Ben Widawsky 2022-02-11 520 if (!state_update) 0184ca5ccb0827 Ben Widawsky 2022-02-11 521 continue; 0184ca5ccb0827 Ben Widawsky 2022-02-11 522 0184ca5ccb0827 Ben Widawsky 2022-02-11 523 if (dev_WARN_ONCE(&cxld->dev, 0184ca5ccb0827 Ben Widawsky 2022-02-11 524 port_grouping >= cxld->nr_targets, 0184ca5ccb0827 Ben Widawsky 2022-02-11 525 "Invalid port grouping %d/%d\n", 0184ca5ccb0827 Ben Widawsky 2022-02-11 526 port_grouping, cxld->nr_targets)) 0184ca5ccb0827 Ben Widawsky 2022-02-11 527 goto err; 0184ca5ccb0827 Ben Widawsky 2022-02-11 528 0184ca5ccb0827 Ben Widawsky 2022-02-11 529 cxld->interleave_ways++; 0184ca5ccb0827 Ben Widawsky 2022-02-11 530 cxld->target[port_grouping] = get_rp(ep); 50b9ca060c8e48 Ben Widawsky 2022-02-11 531 50b9ca060c8e48 Ben Widawsky 2022-02-11 532 /* 50b9ca060c8e48 Ben Widawsky 2022-02-11 533 * At least one switch is connected here if the endpoint 50b9ca060c8e48 Ben Widawsky 2022-02-11 534 * has a depth > 2 50b9ca060c8e48 Ben Widawsky 2022-02-11 535 */ 50b9ca060c8e48 Ben Widawsky 2022-02-11 536 if (ep->port->depth == 2) 50b9ca060c8e48 Ben Widawsky 2022-02-11 537 continue; 50b9ca060c8e48 Ben Widawsky 2022-02-11 538 50b9ca060c8e48 Ben Widawsky 2022-02-11 539 /* Check the staged list to see if this 50b9ca060c8e48 Ben Widawsky 2022-02-11 540 * port has already been added 50b9ca060c8e48 Ben Widawsky 2022-02-11 541 */ 50b9ca060c8e48 Ben Widawsky 2022-02-11 542 switch_port = get_switch(ep); 50b9ca060c8e48 Ben Widawsky 2022-02-11 @543 list_for_each_entry(switch_cxld, &cxlr->staged_list, region_link) { 50b9ca060c8e48 Ben Widawsky 2022-02-11 544 if (to_cxl_port(switch_cxld->dev.parent) == switch_port) 50b9ca060c8e48 Ben Widawsky 2022-02-11 545 found = true; 50b9ca060c8e48 Ben Widawsky 2022-02-11 546 } 50b9ca060c8e48 Ben Widawsky 2022-02-11 547 50b9ca060c8e48 Ben Widawsky 2022-02-11 548 if (found) { 50b9ca060c8e48 Ben Widawsky 2022-02-11 549 target = cxl_find_dport_by_dev(switch_port, ep->dev.parent->parent); 50b9ca060c8e48 Ben Widawsky 2022-02-11 @550 switch_cxld->target[target_ndx++] = target; 50b9ca060c8e48 Ben Widawsky 2022-02-11 551 continue; 50b9ca060c8e48 Ben Widawsky 2022-02-11 552 } 50b9ca060c8e48 Ben Widawsky 2022-02-11 553 50b9ca060c8e48 Ben Widawsky 2022-02-11 554 target_ndx = 0; 50b9ca060c8e48 Ben Widawsky 2022-02-11 555 50b9ca060c8e48 Ben Widawsky 2022-02-11 556 switch_cxld = get_decoder(cxlr, switch_port); 50b9ca060c8e48 Ben Widawsky 2022-02-11 557 switch_cxld->interleave_ways++; 50b9ca060c8e48 Ben Widawsky 2022-02-11 558 switch_cxld->interleave_granularity = cxl_to_ways(region_ig + region_eniw); 00b0519c6f9af5 Ben Widawsky 2022-02-11 559 } 00b0519c6f9af5 Ben Widawsky 2022-02-11 560 } 00b0519c6f9af5 Ben Widawsky 2022-02-11 561 } 00b0519c6f9af5 Ben Widawsky 2022-02-11 562 e3a336d0e7c1ec Ben Widawsky 2022-02-11 563 return true; 5c4ecc7471fee0 Ben Widawsky 2022-02-11 564 5c4ecc7471fee0 Ben Widawsky 2022-02-11 565 err: 5c4ecc7471fee0 Ben Widawsky 2022-02-11 566 dev_dbg(&cxlr->dev, "Couldn't get decoder for region\n"); 5c4ecc7471fee0 Ben Widawsky 2022-02-11 567 list_for_each_entry_safe(cxld, c, &cxlr->staged_list, region_link) 5c4ecc7471fee0 Ben Widawsky 2022-02-11 568 cxl_put_decoder(cxld); 5c4ecc7471fee0 Ben Widawsky 2022-02-11 569 5c4ecc7471fee0 Ben Widawsky 2022-02-11 570 return false; e3a336d0e7c1ec Ben Widawsky 2022-02-11 571 } e3a336d0e7c1ec Ben Widawsky 2022-02-11 572 -- 0-DAY CI Kernel Test Service https://01.org/lkp _______________________________________________ kbuild mailing list -- [email protected] To unsubscribe send an email to [email protected]
