CC: kbuild-...@lists.01.org BCC: l...@intel.com CC: linux-ker...@vger.kernel.org TO: Miquel Raynal <miquel.ray...@bootlin.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: d717180e7f9775d468f415c10a4a474640146001 commit: d8701fe890ecbab239086e7053d62d0f08587d7c mtd: rawnand: renesas: Add new NAND controller driver date: 6 months ago :::::: branch date: 7 hours ago :::::: commit date: 6 months ago config: microblaze-randconfig-m031-20220605 (https://download.01.org/0day-ci/archive/20220606/202206060933.pohn51vu-...@intel.com/config) compiler: microblaze-linux-gcc (GCC) 11.3.0 If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <l...@intel.com> Reported-by: Dan Carpenter <dan.carpen...@oracle.com> smatch warnings: drivers/mtd/nand/raw/renesas-nand-controller.c:900 rnandc_setup_interface() warn: passing a valid pointer to 'PTR_ERR' vim +/PTR_ERR +900 drivers/mtd/nand/raw/renesas-nand-controller.c d8701fe890ecba Miquel Raynal 2021-12-17 888 d8701fe890ecba Miquel Raynal 2021-12-17 889 static int rnandc_setup_interface(struct nand_chip *chip, int chipnr, d8701fe890ecba Miquel Raynal 2021-12-17 890 const struct nand_interface_config *conf) d8701fe890ecba Miquel Raynal 2021-12-17 891 { d8701fe890ecba Miquel Raynal 2021-12-17 892 struct rnand_chip *rnand = to_rnand(chip); d8701fe890ecba Miquel Raynal 2021-12-17 893 struct rnandc *rnandc = to_rnandc(chip->controller); d8701fe890ecba Miquel Raynal 2021-12-17 894 unsigned int period_ns = 1000000000 / clk_get_rate(rnandc->eclk); d8701fe890ecba Miquel Raynal 2021-12-17 895 const struct nand_sdr_timings *sdr; d8701fe890ecba Miquel Raynal 2021-12-17 896 unsigned int cyc, cle, ale, bef_dly, ca_to_data; d8701fe890ecba Miquel Raynal 2021-12-17 897 d8701fe890ecba Miquel Raynal 2021-12-17 898 sdr = nand_get_sdr_timings(conf); d8701fe890ecba Miquel Raynal 2021-12-17 899 if (IS_ERR(sdr)) d8701fe890ecba Miquel Raynal 2021-12-17 @900 return PTR_ERR(sdr); d8701fe890ecba Miquel Raynal 2021-12-17 901 d8701fe890ecba Miquel Raynal 2021-12-17 902 if (sdr->tRP_min != sdr->tWP_min || sdr->tREH_min != sdr->tWH_min) { d8701fe890ecba Miquel Raynal 2021-12-17 903 dev_err(rnandc->dev, "Read and write hold times must be identical\n"); d8701fe890ecba Miquel Raynal 2021-12-17 904 return -EINVAL; d8701fe890ecba Miquel Raynal 2021-12-17 905 } d8701fe890ecba Miquel Raynal 2021-12-17 906 d8701fe890ecba Miquel Raynal 2021-12-17 907 if (chipnr < 0) d8701fe890ecba Miquel Raynal 2021-12-17 908 return 0; d8701fe890ecba Miquel Raynal 2021-12-17 909 d8701fe890ecba Miquel Raynal 2021-12-17 910 rnand->timings_asyn = d8701fe890ecba Miquel Raynal 2021-12-17 911 TIMINGS_ASYN_TRWP(TO_CYCLES64(sdr->tRP_min, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 912 TIMINGS_ASYN_TRWH(TO_CYCLES64(sdr->tREH_min, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 913 rnand->tim_seq0 = d8701fe890ecba Miquel Raynal 2021-12-17 914 TIM_SEQ0_TCCS(TO_CYCLES64(sdr->tCCS_min, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 915 TIM_SEQ0_TADL(TO_CYCLES64(sdr->tADL_min, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 916 TIM_SEQ0_TRHW(TO_CYCLES64(sdr->tRHW_min, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 917 TIM_SEQ0_TWHR(TO_CYCLES64(sdr->tWHR_min, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 918 rnand->tim_seq1 = d8701fe890ecba Miquel Raynal 2021-12-17 919 TIM_SEQ1_TWB(TO_CYCLES64(sdr->tWB_max, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 920 TIM_SEQ1_TRR(TO_CYCLES64(sdr->tRR_min, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 921 TIM_SEQ1_TWW(TO_CYCLES64(sdr->tWW_min, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 922 d8701fe890ecba Miquel Raynal 2021-12-17 923 cyc = sdr->tDS_min + sdr->tDH_min; d8701fe890ecba Miquel Raynal 2021-12-17 924 cle = sdr->tCLH_min + sdr->tCLS_min; d8701fe890ecba Miquel Raynal 2021-12-17 925 ale = sdr->tALH_min + sdr->tALS_min; d8701fe890ecba Miquel Raynal 2021-12-17 926 bef_dly = sdr->tWB_max - sdr->tDH_min; d8701fe890ecba Miquel Raynal 2021-12-17 927 ca_to_data = sdr->tWHR_min + sdr->tREA_max - sdr->tDH_min; d8701fe890ecba Miquel Raynal 2021-12-17 928 d8701fe890ecba Miquel Raynal 2021-12-17 929 /* d8701fe890ecba Miquel Raynal 2021-12-17 930 * D0 = CMD -> ADDR = tCLH + tCLS - 1 cycle d8701fe890ecba Miquel Raynal 2021-12-17 931 * D1 = CMD -> CMD = tCLH + tCLS - 1 cycle d8701fe890ecba Miquel Raynal 2021-12-17 932 * D2 = CMD -> DLY = tWB - tDH d8701fe890ecba Miquel Raynal 2021-12-17 933 * D3 = CMD -> DATA = tWHR + tREA - tDH d8701fe890ecba Miquel Raynal 2021-12-17 934 */ d8701fe890ecba Miquel Raynal 2021-12-17 935 rnand->tim_gen_seq0 = d8701fe890ecba Miquel Raynal 2021-12-17 936 TIM_GEN_SEQ0_D0(TO_CYCLES64(cle - cyc, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 937 TIM_GEN_SEQ0_D1(TO_CYCLES64(cle - cyc, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 938 TIM_GEN_SEQ0_D2(TO_CYCLES64(bef_dly, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 939 TIM_GEN_SEQ0_D3(TO_CYCLES64(ca_to_data, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 940 d8701fe890ecba Miquel Raynal 2021-12-17 941 /* d8701fe890ecba Miquel Raynal 2021-12-17 942 * D4 = ADDR -> CMD = tALH + tALS - 1 cyle d8701fe890ecba Miquel Raynal 2021-12-17 943 * D5 = ADDR -> ADDR = tALH + tALS - 1 cyle d8701fe890ecba Miquel Raynal 2021-12-17 944 * D6 = ADDR -> DLY = tWB - tDH d8701fe890ecba Miquel Raynal 2021-12-17 945 * D7 = ADDR -> DATA = tWHR + tREA - tDH d8701fe890ecba Miquel Raynal 2021-12-17 946 */ d8701fe890ecba Miquel Raynal 2021-12-17 947 rnand->tim_gen_seq1 = d8701fe890ecba Miquel Raynal 2021-12-17 948 TIM_GEN_SEQ1_D4(TO_CYCLES64(ale - cyc, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 949 TIM_GEN_SEQ1_D5(TO_CYCLES64(ale - cyc, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 950 TIM_GEN_SEQ1_D6(TO_CYCLES64(bef_dly, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 951 TIM_GEN_SEQ1_D7(TO_CYCLES64(ca_to_data, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 952 d8701fe890ecba Miquel Raynal 2021-12-17 953 /* d8701fe890ecba Miquel Raynal 2021-12-17 954 * D8 = DLY -> DATA = tRR + tREA d8701fe890ecba Miquel Raynal 2021-12-17 955 * D9 = DLY -> CMD = tRR d8701fe890ecba Miquel Raynal 2021-12-17 956 * D10 = DATA -> CMD = tCLH + tCLS - 1 cycle d8701fe890ecba Miquel Raynal 2021-12-17 957 * D11 = DATA -> DLY = tWB - tDH d8701fe890ecba Miquel Raynal 2021-12-17 958 */ d8701fe890ecba Miquel Raynal 2021-12-17 959 rnand->tim_gen_seq2 = d8701fe890ecba Miquel Raynal 2021-12-17 960 TIM_GEN_SEQ2_D8(TO_CYCLES64(sdr->tRR_min + sdr->tREA_max, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 961 TIM_GEN_SEQ2_D9(TO_CYCLES64(sdr->tRR_min, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 962 TIM_GEN_SEQ2_D10(TO_CYCLES64(cle - cyc, period_ns)) | d8701fe890ecba Miquel Raynal 2021-12-17 963 TIM_GEN_SEQ2_D11(TO_CYCLES64(bef_dly, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 964 d8701fe890ecba Miquel Raynal 2021-12-17 965 /* D12 = DATA -> END = tCLH - tDH */ d8701fe890ecba Miquel Raynal 2021-12-17 966 rnand->tim_gen_seq3 = d8701fe890ecba Miquel Raynal 2021-12-17 967 TIM_GEN_SEQ3_D12(TO_CYCLES64(sdr->tCLH_min - sdr->tDH_min, period_ns)); d8701fe890ecba Miquel Raynal 2021-12-17 968 d8701fe890ecba Miquel Raynal 2021-12-17 969 return 0; d8701fe890ecba Miquel Raynal 2021-12-17 970 } d8701fe890ecba Miquel Raynal 2021-12-17 971 -- 0-DAY CI Kernel Test Service https://01.org/lkp _______________________________________________ kbuild mailing list -- kbuild@lists.01.org To unsubscribe send an email to kbuild-le...@lists.01.org
