CC: kbuild-...@lists.01.org BCC: l...@intel.com CC: Alison Schofield <alison.schofi...@intel.com> CC: Vishal Verma <vishal.l.ve...@intel.com> CC: Ira Weiny <ira.we...@intel.com> CC: Ben Widawsky <ben.widaw...@intel.com> CC: Dan Williams <dan.j.willi...@intel.com> TO: Dan Williams <dan.j.willi...@intel.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git preview head: 1985cf58850562e4b960e19d46f0d8f19d6c7cbd commit: 6736e0edd378fb84365af650a50859e95ea1a29a [46/51] cxl/region: Program target lists :::::: branch date: 10 days ago :::::: commit date: 10 days ago config: i386-randconfig-m021-20220704 (https://download.01.org/0day-ci/archive/20220705/202207050524.7pnw87fk-...@intel.com/config) compiler: gcc-11 (Debian 11.3.0-3) 11.3.0 If you fix the issue, kindly add following tag where applicable Reported-by: kernel test robot <l...@intel.com> Reported-by: Dan Carpenter <dan.carpen...@oracle.com> New smatch warnings: drivers/cxl/core/region.c:807 cxl_port_setup_targets() error: uninitialized symbol 'peig'. drivers/cxl/core/region.c:807 cxl_port_setup_targets() error: uninitialized symbol 'peiw'. drivers/cxl/core/region.c:807 cxl_port_setup_targets() error: uninitialized symbol 'eiw'. Old smatch warnings: drivers/cxl/core/region.c:281 alloc_hpa() error: uninitialized symbol 'res'. drivers/cxl/core/region.c:811 cxl_port_setup_targets() error: uninitialized symbol 'peiw'. drivers/cxl/core/region.c:812 cxl_port_setup_targets() error: uninitialized symbol 'peig'. drivers/cxl/core/region.c:1388 create_pmem_region_store() warn: unsigned 'rc' is never less than zero. vim +/peig +807 drivers/cxl/core/region.c 6736e0edd378fb8 Dan Williams 2022-06-06 738 6736e0edd378fb8 Dan Williams 2022-06-06 739 static int cxl_port_setup_targets(struct cxl_port *port, 6736e0edd378fb8 Dan Williams 2022-06-06 740 struct cxl_region *cxlr, 6736e0edd378fb8 Dan Williams 2022-06-06 741 struct cxl_endpoint_decoder *cxled) 6736e0edd378fb8 Dan Williams 2022-06-06 742 { 6736e0edd378fb8 Dan Williams 2022-06-06 743 struct cxl_root_decoder *cxlrd = to_cxl_root_decoder(cxlr->dev.parent); 6736e0edd378fb8 Dan Williams 2022-06-06 744 int parent_iw, parent_ig, ig, iw, rc, inc = 0, pos = cxled->pos; 6736e0edd378fb8 Dan Williams 2022-06-06 745 struct cxl_port *parent_port = to_cxl_port(port->dev.parent); 6736e0edd378fb8 Dan Williams 2022-06-06 746 struct cxl_region_ref *cxl_rr = cxl_rr_load(port, cxlr); 6736e0edd378fb8 Dan Williams 2022-06-06 747 struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); 6736e0edd378fb8 Dan Williams 2022-06-06 748 struct cxl_ep *ep = cxl_ep_load(port, cxlmd); 6736e0edd378fb8 Dan Williams 2022-06-06 749 struct cxl_region_params *p = &cxlr->params; 6736e0edd378fb8 Dan Williams 2022-06-06 750 struct cxl_decoder *cxld = cxl_rr->decoder; 6736e0edd378fb8 Dan Williams 2022-06-06 751 struct cxl_switch_decoder *cxlsd; 6736e0edd378fb8 Dan Williams 2022-06-06 752 u16 eig, peig; 6736e0edd378fb8 Dan Williams 2022-06-06 753 u8 eiw, peiw; 6736e0edd378fb8 Dan Williams 2022-06-06 754 6736e0edd378fb8 Dan Williams 2022-06-06 755 /* 6736e0edd378fb8 Dan Williams 2022-06-06 756 * While root level decoders support x3, x6, x12, switch level 6736e0edd378fb8 Dan Williams 2022-06-06 757 * decoders only support powers of 2 up to x16. 6736e0edd378fb8 Dan Williams 2022-06-06 758 */ 6736e0edd378fb8 Dan Williams 2022-06-06 759 if (!is_power_of_2(cxl_rr->nr_targets)) { 6736e0edd378fb8 Dan Williams 2022-06-06 760 dev_dbg(&cxlr->dev, "%s:%s: invalid target count %d\n", 6736e0edd378fb8 Dan Williams 2022-06-06 761 dev_name(port->uport), dev_name(&port->dev), 6736e0edd378fb8 Dan Williams 2022-06-06 762 cxl_rr->nr_targets); 6736e0edd378fb8 Dan Williams 2022-06-06 763 return -EINVAL; 6736e0edd378fb8 Dan Williams 2022-06-06 764 } 6736e0edd378fb8 Dan Williams 2022-06-06 765 6736e0edd378fb8 Dan Williams 2022-06-06 766 cxlsd = to_cxl_switch_decoder(&cxld->dev); 6736e0edd378fb8 Dan Williams 2022-06-06 767 if (cxl_rr->nr_targets_set) { 6736e0edd378fb8 Dan Williams 2022-06-06 768 int i, distance; 6736e0edd378fb8 Dan Williams 2022-06-06 769 6736e0edd378fb8 Dan Williams 2022-06-06 770 distance = p->nr_targets / cxl_rr->nr_targets; 6736e0edd378fb8 Dan Williams 2022-06-06 771 for (i = 0; i < cxl_rr->nr_targets_set; i++) 6736e0edd378fb8 Dan Williams 2022-06-06 772 if (ep->dport == cxlsd->target[i]) { 6736e0edd378fb8 Dan Williams 2022-06-06 773 rc = check_last_peer(cxled, ep, cxl_rr, 6736e0edd378fb8 Dan Williams 2022-06-06 774 distance); 6736e0edd378fb8 Dan Williams 2022-06-06 775 if (rc) 6736e0edd378fb8 Dan Williams 2022-06-06 776 return rc; 6736e0edd378fb8 Dan Williams 2022-06-06 777 goto out_target_set; 6736e0edd378fb8 Dan Williams 2022-06-06 778 } 6736e0edd378fb8 Dan Williams 2022-06-06 779 goto add_target; 6736e0edd378fb8 Dan Williams 2022-06-06 780 } 6736e0edd378fb8 Dan Williams 2022-06-06 781 6736e0edd378fb8 Dan Williams 2022-06-06 782 if (is_cxl_root(parent_port)) { 6736e0edd378fb8 Dan Williams 2022-06-06 783 parent_ig = cxlrd->cxlsd.cxld.interleave_granularity; 6736e0edd378fb8 Dan Williams 2022-06-06 784 parent_iw = cxlrd->cxlsd.cxld.interleave_ways; 6736e0edd378fb8 Dan Williams 2022-06-06 785 /* 6736e0edd378fb8 Dan Williams 2022-06-06 786 * For purposes of address bit routing, use power-of-2 math for 6736e0edd378fb8 Dan Williams 2022-06-06 787 * switch ports. 6736e0edd378fb8 Dan Williams 2022-06-06 788 */ 6736e0edd378fb8 Dan Williams 2022-06-06 789 if (!is_power_of_2(parent_iw)) 6736e0edd378fb8 Dan Williams 2022-06-06 790 parent_iw /= 3; 6736e0edd378fb8 Dan Williams 2022-06-06 791 } else { 6736e0edd378fb8 Dan Williams 2022-06-06 792 struct cxl_region_ref *parent_rr; 6736e0edd378fb8 Dan Williams 2022-06-06 793 struct cxl_decoder *parent_cxld; 6736e0edd378fb8 Dan Williams 2022-06-06 794 6736e0edd378fb8 Dan Williams 2022-06-06 795 parent_rr = cxl_rr_load(parent_port, cxlr); 6736e0edd378fb8 Dan Williams 2022-06-06 796 parent_cxld = parent_rr->decoder; 6736e0edd378fb8 Dan Williams 2022-06-06 797 parent_ig = parent_cxld->interleave_granularity; 6736e0edd378fb8 Dan Williams 2022-06-06 798 parent_iw = parent_cxld->interleave_ways; 6736e0edd378fb8 Dan Williams 2022-06-06 799 } 6736e0edd378fb8 Dan Williams 2022-06-06 800 6736e0edd378fb8 Dan Williams 2022-06-06 801 granularity_to_cxl(parent_ig, &peig); 6736e0edd378fb8 Dan Williams 2022-06-06 802 ways_to_cxl(parent_iw, &peiw); 6736e0edd378fb8 Dan Williams 2022-06-06 803 6736e0edd378fb8 Dan Williams 2022-06-06 804 iw = cxl_rr->nr_targets; 6736e0edd378fb8 Dan Williams 2022-06-06 805 ways_to_cxl(iw, &eiw); 6736e0edd378fb8 Dan Williams 2022-06-06 806 if (cxl_rr->nr_targets > 1) { 6736e0edd378fb8 Dan Williams 2022-06-06 @807 u32 address_bit = max(peig + peiw, eiw + peig); 6736e0edd378fb8 Dan Williams 2022-06-06 808 6736e0edd378fb8 Dan Williams 2022-06-06 809 eig = address_bit - eiw + 1; 6736e0edd378fb8 Dan Williams 2022-06-06 810 } else { 6736e0edd378fb8 Dan Williams 2022-06-06 811 eiw = peiw; 6736e0edd378fb8 Dan Williams 2022-06-06 812 eig = peig; 6736e0edd378fb8 Dan Williams 2022-06-06 813 } 6736e0edd378fb8 Dan Williams 2022-06-06 814 6736e0edd378fb8 Dan Williams 2022-06-06 815 rc = cxl_to_granularity(eig, &ig); 6736e0edd378fb8 Dan Williams 2022-06-06 816 if (rc) { 6736e0edd378fb8 Dan Williams 2022-06-06 817 dev_dbg(&cxlr->dev, "%s:%s: invalid interleave: %d\n", 6736e0edd378fb8 Dan Williams 2022-06-06 818 dev_name(port->uport), dev_name(&port->dev), 6736e0edd378fb8 Dan Williams 2022-06-06 819 256 << eig); 6736e0edd378fb8 Dan Williams 2022-06-06 820 return rc; 6736e0edd378fb8 Dan Williams 2022-06-06 821 } 6736e0edd378fb8 Dan Williams 2022-06-06 822 6736e0edd378fb8 Dan Williams 2022-06-06 823 cxld->interleave_ways = iw; 6736e0edd378fb8 Dan Williams 2022-06-06 824 cxld->interleave_granularity = ig; 6736e0edd378fb8 Dan Williams 2022-06-06 825 dev_dbg(&cxlr->dev, "%s:%s iw: %d ig: %d\n", dev_name(port->uport), 6736e0edd378fb8 Dan Williams 2022-06-06 826 dev_name(&port->dev), iw, ig); 6736e0edd378fb8 Dan Williams 2022-06-06 827 add_target: 6736e0edd378fb8 Dan Williams 2022-06-06 828 if (cxl_rr->nr_targets_set == cxl_rr->nr_targets) { 6736e0edd378fb8 Dan Williams 2022-06-06 829 dev_dbg(&cxlr->dev, 6736e0edd378fb8 Dan Williams 2022-06-06 830 "%s:%s: targets full trying to add %s:%s at %d\n", 6736e0edd378fb8 Dan Williams 2022-06-06 831 dev_name(port->uport), dev_name(&port->dev), 6736e0edd378fb8 Dan Williams 2022-06-06 832 dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); 6736e0edd378fb8 Dan Williams 2022-06-06 833 return -ENXIO; 6736e0edd378fb8 Dan Williams 2022-06-06 834 } 6736e0edd378fb8 Dan Williams 2022-06-06 835 cxlsd->target[cxl_rr->nr_targets_set] = ep->dport; 6736e0edd378fb8 Dan Williams 2022-06-06 836 inc = 1; 6736e0edd378fb8 Dan Williams 2022-06-06 837 out_target_set: 6736e0edd378fb8 Dan Williams 2022-06-06 838 cxl_rr->nr_targets_set += inc; 6736e0edd378fb8 Dan Williams 2022-06-06 839 dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n", 6736e0edd378fb8 Dan Williams 2022-06-06 840 dev_name(port->uport), dev_name(&port->dev), 6736e0edd378fb8 Dan Williams 2022-06-06 841 cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport), 6736e0edd378fb8 Dan Williams 2022-06-06 842 dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); 6736e0edd378fb8 Dan Williams 2022-06-06 843 6736e0edd378fb8 Dan Williams 2022-06-06 844 return 0; 6736e0edd378fb8 Dan Williams 2022-06-06 845 } 6736e0edd378fb8 Dan Williams 2022-06-06 846 -- 0-DAY CI Kernel Test Service https://01.org/lkp _______________________________________________ kbuild mailing list -- kbuild@lists.01.org To unsubscribe send an email to kbuild-le...@lists.01.org
