:::::: 
:::::: Manual check reason: "low confidence static check warning: 
drivers/clk/baikal-t1/clk-ccu-div.c:354:42: warning: Boolean result is used in 
bitwise operation. Clarify expression with parentheses. [clarifyCondition]"
:::::: 

BCC: [email protected]
CC: [email protected]
In-Reply-To: <[email protected]>
References: <[email protected]>
TO: Serge Semin <[email protected]>
TO: Stephen Boyd <[email protected]>
TO: Michael Turquette <[email protected]>
CC: Serge Semin <[email protected]>
CC: Alexey Malahov <[email protected]>
CC: Pavel Parkhomenko <[email protected]>
CC: Philipp Zabel <[email protected]>
CC: Thomas Bogendoerfer <[email protected]>
CC: [email protected]
CC: [email protected]
CC: [email protected]

Hi Serge,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on pza/reset/next linus/master v6.0-rc3 next-20220831]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    
https://github.com/intel-lab-lkp/linux/commits/Serge-Semin/clk-resets-baikal-t1-Add-DDR-PCIe-resets-and-xGMAC-SATA-fixes/20220823-023308
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
:::::: branch date: 9 days ago
:::::: commit date: 9 days ago
compiler: or1k-linux-gcc (GCC) 12.1.0
reproduce (cppcheck warning):
        # apt-get install cppcheck
        git checkout 8adbd3c7fa1d8cf71c65ccbd315727a3cebf67e4
        cppcheck --quiet --enable=style,performance,portability --template=gcc 
FILE

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>


cppcheck possible warnings: (new ones prefixed by >>, may not real problems)

>> drivers/clk/baikal-t1/clk-ccu-div.c:354:42: warning: Boolean result is used 
>> in bitwise operation. Clarify expression with parentheses. [clarifyCondition]
     if (!!(info->features & CCU_DIV_BASIC) ^ defer) {
                                            ^
   drivers/clk/baikal-t1/clk-ccu-div.c:397:57: warning: Boolean result is used 
in bitwise operation. Clarify expression with parentheses. [clarifyCondition]
     if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
                                                           ^
   drivers/clk/baikal-t1/clk-ccu-div.c:412:57: warning: Boolean result is used 
in bitwise operation. Clarify expression with parentheses. [clarifyCondition]
     if (!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
                                                           ^

vim +354 drivers/clk/baikal-t1/clk-ccu-div.c

353afa3a8d2ef4 Serge Semin 2020-05-27  345  
8adbd3c7fa1d8c Serge Semin 2022-08-22  346  static int 
ccu_div_clk_register(struct ccu_div_data *data, bool defer)
353afa3a8d2ef4 Serge Semin 2020-05-27  347  {
353afa3a8d2ef4 Serge Semin 2020-05-27  348      int idx, ret;
353afa3a8d2ef4 Serge Semin 2020-05-27  349  
353afa3a8d2ef4 Serge Semin 2020-05-27  350      for (idx = 0; idx < 
data->divs_num; ++idx) {
353afa3a8d2ef4 Serge Semin 2020-05-27  351              const struct 
ccu_div_info *info = &data->divs_info[idx];
353afa3a8d2ef4 Serge Semin 2020-05-27  352              struct 
ccu_div_init_data init = {0};
353afa3a8d2ef4 Serge Semin 2020-05-27  353  
8adbd3c7fa1d8c Serge Semin 2022-08-22 @354              if (!!(info->features & 
CCU_DIV_BASIC) ^ defer) {
8adbd3c7fa1d8c Serge Semin 2022-08-22  355                      if 
(!data->divs[idx])
8adbd3c7fa1d8c Serge Semin 2022-08-22  356                              
data->divs[idx] = ERR_PTR(-EPROBE_DEFER);
8adbd3c7fa1d8c Serge Semin 2022-08-22  357  
8adbd3c7fa1d8c Serge Semin 2022-08-22  358                      continue;
8adbd3c7fa1d8c Serge Semin 2022-08-22  359              }
8adbd3c7fa1d8c Serge Semin 2022-08-22  360  
353afa3a8d2ef4 Serge Semin 2020-05-27  361              init.id = info->id;
353afa3a8d2ef4 Serge Semin 2020-05-27  362              init.name = info->name;
353afa3a8d2ef4 Serge Semin 2020-05-27  363              init.parent_name = 
info->parent_name;
353afa3a8d2ef4 Serge Semin 2020-05-27  364              init.np = data->np;
353afa3a8d2ef4 Serge Semin 2020-05-27  365              init.type = info->type;
353afa3a8d2ef4 Serge Semin 2020-05-27  366              init.flags = 
info->flags;
353afa3a8d2ef4 Serge Semin 2020-05-27  367              init.features = 
info->features;
353afa3a8d2ef4 Serge Semin 2020-05-27  368  
353afa3a8d2ef4 Serge Semin 2020-05-27  369              if (init.type == 
CCU_DIV_VAR) {
353afa3a8d2ef4 Serge Semin 2020-05-27  370                      init.base = 
info->base;
353afa3a8d2ef4 Serge Semin 2020-05-27  371                      init.sys_regs = 
data->sys_regs;
353afa3a8d2ef4 Serge Semin 2020-05-27  372                      init.width = 
info->width;
353afa3a8d2ef4 Serge Semin 2020-05-27  373              } else if (init.type == 
CCU_DIV_GATE) {
353afa3a8d2ef4 Serge Semin 2020-05-27  374                      init.base = 
info->base;
353afa3a8d2ef4 Serge Semin 2020-05-27  375                      init.sys_regs = 
data->sys_regs;
353afa3a8d2ef4 Serge Semin 2020-05-27  376                      init.divider = 
info->divider;
989712dc656f8e Serge Semin 2022-08-22  377              } else if (init.type == 
CCU_DIV_BUF) {
989712dc656f8e Serge Semin 2022-08-22  378                      init.base = 
info->base;
989712dc656f8e Serge Semin 2022-08-22  379                      init.sys_regs = 
data->sys_regs;
353afa3a8d2ef4 Serge Semin 2020-05-27  380              } else {
353afa3a8d2ef4 Serge Semin 2020-05-27  381                      init.divider = 
info->divider;
353afa3a8d2ef4 Serge Semin 2020-05-27  382              }
353afa3a8d2ef4 Serge Semin 2020-05-27  383  
353afa3a8d2ef4 Serge Semin 2020-05-27  384              data->divs[idx] = 
ccu_div_hw_register(&init);
353afa3a8d2ef4 Serge Semin 2020-05-27  385              if 
(IS_ERR(data->divs[idx])) {
353afa3a8d2ef4 Serge Semin 2020-05-27  386                      ret = 
PTR_ERR(data->divs[idx]);
353afa3a8d2ef4 Serge Semin 2020-05-27  387                      
pr_err("Couldn't register divider '%s' hw\n",
353afa3a8d2ef4 Serge Semin 2020-05-27  388                              
init.name);
353afa3a8d2ef4 Serge Semin 2020-05-27  389                      goto 
err_hw_unregister;
353afa3a8d2ef4 Serge Semin 2020-05-27  390              }
353afa3a8d2ef4 Serge Semin 2020-05-27  391      }
353afa3a8d2ef4 Serge Semin 2020-05-27  392  
353afa3a8d2ef4 Serge Semin 2020-05-27  393      return 0;
353afa3a8d2ef4 Serge Semin 2020-05-27  394  
353afa3a8d2ef4 Serge Semin 2020-05-27  395  err_hw_unregister:
8adbd3c7fa1d8c Serge Semin 2022-08-22  396      for (--idx; idx >= 0; --idx) {
8adbd3c7fa1d8c Serge Semin 2022-08-22  397              if 
(!!(data->divs_info[idx].features & CCU_DIV_BASIC) ^ defer)
8adbd3c7fa1d8c Serge Semin 2022-08-22  398                      continue;
8adbd3c7fa1d8c Serge Semin 2022-08-22  399  
353afa3a8d2ef4 Serge Semin 2020-05-27  400              
ccu_div_hw_unregister(data->divs[idx]);
8adbd3c7fa1d8c Serge Semin 2022-08-22  401      }
353afa3a8d2ef4 Serge Semin 2020-05-27  402  
353afa3a8d2ef4 Serge Semin 2020-05-27  403      return ret;
353afa3a8d2ef4 Serge Semin 2020-05-27  404  }
353afa3a8d2ef4 Serge Semin 2020-05-27  405  

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